PPC4xx Clock Power Management (CPM) node

Required properties:
	- compatible		: compatible list, currently only "ibm,cpm"
	- dcr-access-method	: "native"
	- dcr-reg		: < DCR register range >

Optional properties:
	- er-offset		: All 4xx SoCs with a CPM controller have
				  one of two different order for the CPM
				  registers. Some have the CPM registers
				  in the following order (ER,FR,SR). The
				  others have them in the following order
				  (SR,ER,FR). For the second case set
				  er-offset = <1>.
	- unused-units		: specifier consist of one cell. For each
				  bit in the cell, the corresponding bit
				  in CPM will be set to turn off unused
				  devices.
	- idle-doze		: specifier consist of one cell. For each
				  bit in the cell, the corresponding bit
				  in CPM will be set to turn off unused
				  devices. This is usually just CPM[CPU].
	- standby		: specifier consist of one cell. For each
				  bit in the cell, the corresponding bit
				  in CPM will be set on standby and
				  restored on resume.
	- suspend		: specifier consist of one cell. For each
				  bit in the cell, the corresponding bit
				  in CPM will be set on suspend (mem) and
				  restored on resume. Note, for standby
				  and suspend the corresponding bits can
				  be different or the same. Usually for
				  standby only class 2 and 3 units are set.
				  However, the interface does not care.
				  If they are the same, the additional
				  power saving will be seeing if support
				  is available to put the DDR in self
				  refresh mode and any additional power
				  saving techniques for the specific SoC.

Example:
	CPM0: cpm {
		compatible = "ibm,cpm";
		dcr-access-method = "native";
		dcr-reg = <0x160 0x003>;
		er-offset = <0>;
		unused-units = <0x00000100>;
		idle-doze = <0x02000000>;
		standby = <0xfeff0000>;
		suspend = <0xfeff791d>;
};
