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<p style="position:absolute;top:1103px;left:761px;white-space:nowrap" class="ft00">Vol. 3C&#160;35-79</p>
<p style="position:absolute;top:47px;left:633px;white-space:nowrap" class="ft01">MODEL-SPECIFIC REGISTERS (MSRS)</p>
<p style="position:absolute;top:189px;left:186px;white-space:nowrap" class="ft02">7</p>
<p style="position:absolute;top:189px;left:358px;white-space:nowrap" class="ft02">Core</p>
<p style="position:absolute;top:189px;left:450px;white-space:nowrap" class="ft04">Performance&#160;Monitoring Available (R)&#160;<br/>Se<a href="o_fe12b1e2a880e0ce-1283.html">e Table&#160;35-2.</a></p>
<p style="position:absolute;top:234px;left:186px;white-space:nowrap" class="ft02">10:8</p>
<p style="position:absolute;top:234px;left:450px;white-space:nowrap" class="ft02">Reserved.</p>
<p style="position:absolute;top:258px;left:186px;white-space:nowrap" class="ft02">11</p>
<p style="position:absolute;top:258px;left:358px;white-space:nowrap" class="ft02">Core</p>
<p style="position:absolute;top:258px;left:450px;white-space:nowrap" class="ft04">Branch&#160;Trace Storage Unavailable (RO)&#160;<br/>Se<a href="o_fe12b1e2a880e0ce-1283.html">e Table&#160;35-2.</a></p>
<p style="position:absolute;top:303px;left:186px;white-space:nowrap" class="ft02">12</p>
<p style="position:absolute;top:303px;left:358px;white-space:nowrap" class="ft02">Core</p>
<p style="position:absolute;top:303px;left:450px;white-space:nowrap" class="ft04">Processor Event Based&#160;Sampling Unavailable (RO)&#160;<br/>Se<a href="o_fe12b1e2a880e0ce-1283.html">e Table&#160;35-2.</a></p>
<p style="position:absolute;top:348px;left:186px;white-space:nowrap" class="ft02">15:13</p>
<p style="position:absolute;top:348px;left:450px;white-space:nowrap" class="ft02">Reserved.</p>
<p style="position:absolute;top:371px;left:186px;white-space:nowrap" class="ft02">16</p>
<p style="position:absolute;top:371px;left:358px;white-space:nowrap" class="ft02">Module</p>
<p style="position:absolute;top:371px;left:450px;white-space:nowrap" class="ft05">Enhanced&#160;Intel SpeedStep&#160;Technology&#160;Enable (R/W)&#160;<br/>Se<a href="o_fe12b1e2a880e0ce-1283.html">e Table&#160;35-2.</a></p>
<p style="position:absolute;top:417px;left:186px;white-space:nowrap" class="ft02">18</p>
<p style="position:absolute;top:417px;left:358px;white-space:nowrap" class="ft02">Core</p>
<p style="position:absolute;top:417px;left:450px;white-space:nowrap" class="ft04">ENABLE&#160;MONITOR FSM&#160;(R/W)&#160;<br/>Se<a href="o_fe12b1e2a880e0ce-1283.html">e Table&#160;35-2.</a></p>
<p style="position:absolute;top:462px;left:186px;white-space:nowrap" class="ft02">21:19</p>
<p style="position:absolute;top:462px;left:450px;white-space:nowrap" class="ft02">Reserved.</p>
<p style="position:absolute;top:485px;left:186px;white-space:nowrap" class="ft02">22</p>
<p style="position:absolute;top:485px;left:358px;white-space:nowrap" class="ft02">Core</p>
<p style="position:absolute;top:485px;left:450px;white-space:nowrap" class="ft05">Limit CPUID&#160;Maxval (R/W)&#160;<br/>Se<a href="o_fe12b1e2a880e0ce-1283.html">e Table&#160;35-2.</a></p>
<p style="position:absolute;top:530px;left:186px;white-space:nowrap" class="ft02">23</p>
<p style="position:absolute;top:530px;left:358px;white-space:nowrap" class="ft02">Module</p>
<p style="position:absolute;top:530px;left:450px;white-space:nowrap" class="ft05">xTPR&#160;Message Disable (R/W)&#160;<br/>Se<a href="o_fe12b1e2a880e0ce-1283.html">e Table&#160;35-2.</a></p>
<p style="position:absolute;top:575px;left:186px;white-space:nowrap" class="ft02">33:24</p>
<p style="position:absolute;top:575px;left:450px;white-space:nowrap" class="ft02">Reserved.</p>
<p style="position:absolute;top:600px;left:186px;white-space:nowrap" class="ft02">34</p>
<p style="position:absolute;top:600px;left:358px;white-space:nowrap" class="ft02">Core</p>
<p style="position:absolute;top:600px;left:450px;white-space:nowrap" class="ft04">XD&#160;Bit Disable (R/W)&#160;<br/>Se<a href="o_fe12b1e2a880e0ce-1283.html">e Table&#160;35-2.</a></p>
<p style="position:absolute;top:645px;left:186px;white-space:nowrap" class="ft02">37:35</p>
<p style="position:absolute;top:645px;left:450px;white-space:nowrap" class="ft02">Reserved.</p>
<p style="position:absolute;top:669px;left:186px;white-space:nowrap" class="ft02">38</p>
<p style="position:absolute;top:669px;left:358px;white-space:nowrap" class="ft02">Module</p>
<p style="position:absolute;top:669px;left:450px;white-space:nowrap" class="ft04">Turbo&#160;Mode&#160;Disable&#160;(R/W)<br/>When set to&#160;1 on&#160;processors&#160;that&#160;support Intel Turbo Boost&#160;</p>
<p style="position:absolute;top:706px;left:450px;white-space:nowrap" class="ft02">Technology,&#160;the turbo mode&#160;feature&#160;is&#160;disabled&#160;and&#160;the&#160;IDA_Enable&#160;</p>
<p style="position:absolute;top:723px;left:450px;white-space:nowrap" class="ft04">feature flag will be clear (CPUID.06H: EAX[1]=0).<br/>When set to&#160;a 0 on processors&#160;that&#160;support IDA,&#160;CPUID.06H:&#160;</p>
<p style="position:absolute;top:760px;left:450px;white-space:nowrap" class="ft05">EAX[1]&#160;reports&#160;the processor’s support of&#160;turbo mode&#160;is&#160;enabled.<br/>Note:&#160;the power-on default value is used by BIOS to&#160;detect&#160;</p>
<p style="position:absolute;top:798px;left:450px;white-space:nowrap" class="ft02">hardware&#160;support of&#160;turbo mode.&#160;If power-on default value is 1,&#160;</p>
<p style="position:absolute;top:814px;left:450px;white-space:nowrap" class="ft02">turbo mode&#160;is available in&#160;the processor.&#160;If power-on&#160;default value&#160;</p>
<p style="position:absolute;top:831px;left:450px;white-space:nowrap" class="ft02">is 0,&#160;turbo&#160;mode&#160;is not available.</p>
<p style="position:absolute;top:854px;left:186px;white-space:nowrap" class="ft02">63:39</p>
<p style="position:absolute;top:854px;left:450px;white-space:nowrap" class="ft02">Reserved.</p>
<p style="position:absolute;top:879px;left:81px;white-space:nowrap" class="ft02">1C8H</p>
<p style="position:absolute;top:879px;left:141px;white-space:nowrap" class="ft02">456</p>
<p style="position:absolute;top:879px;left:186px;white-space:nowrap" class="ft02">MSR_LBR_SELECT</p>
<p style="position:absolute;top:879px;left:358px;white-space:nowrap" class="ft02">Core</p>
<p style="position:absolute;top:879px;left:450px;white-space:nowrap" class="ft04">Last&#160;Branch&#160;Record&#160;Filtering&#160;Select&#160;Register&#160;(R/W)&#160;<br/>See<a href="o_fe12b1e2a880e0ce-602.html">&#160;Section&#160;17.7.2, “Filtering&#160;of&#160;Last&#160;Branch&#160;Records.”</a></p>
<p style="position:absolute;top:924px;left:186px;white-space:nowrap" class="ft02">0</p>
<p style="position:absolute;top:924px;left:450px;white-space:nowrap" class="ft02">CPL_EQ_0</p>
<p style="position:absolute;top:948px;left:186px;white-space:nowrap" class="ft02">1</p>
<p style="position:absolute;top:948px;left:450px;white-space:nowrap" class="ft02">CPL_NEQ_0</p>
<p style="position:absolute;top:971px;left:186px;white-space:nowrap" class="ft02">2</p>
<p style="position:absolute;top:971px;left:450px;white-space:nowrap" class="ft02">JCC</p>
<p style="position:absolute;top:996px;left:186px;white-space:nowrap" class="ft02">3</p>
<p style="position:absolute;top:996px;left:450px;white-space:nowrap" class="ft02">NEAR_REL_CALL</p>
<p style="position:absolute;top:1020px;left:186px;white-space:nowrap" class="ft02">4</p>
<p style="position:absolute;top:1020px;left:450px;white-space:nowrap" class="ft02">NEAR_IND_CALL</p>
<p style="position:absolute;top:1043px;left:186px;white-space:nowrap" class="ft02">5</p>
<p style="position:absolute;top:1043px;left:450px;white-space:nowrap" class="ft02">NEAR_RET</p>
<p style="position:absolute;top:100px;left:194px;white-space:nowrap" class="ft03">Table&#160;35-7.&#160;&#160;MSRs&#160;Common to&#160;the&#160;Silvermont&#160;and&#160;Airmont Microarchitectures&#160;</p>
<p style="position:absolute;top:124px;left:99px;white-space:nowrap" class="ft02">Register&#160;</p>
<p style="position:absolute;top:141px;left:100px;white-space:nowrap" class="ft02">Address</p>
<p style="position:absolute;top:141px;left:222px;white-space:nowrap" class="ft02">Register Name</p>
<p style="position:absolute;top:124px;left:380px;white-space:nowrap" class="ft02">Scope</p>
<p style="position:absolute;top:141px;left:595px;white-space:nowrap" class="ft02">Bit&#160;Description</p>
<p style="position:absolute;top:164px;left:83px;white-space:nowrap" class="ft02">&#160;Hex</p>
<p style="position:absolute;top:164px;left:141px;white-space:nowrap" class="ft02">Dec</p>
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