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<p style="position:absolute;top:1103px;left:775px;white-space:nowrap" class="ft00">Vol. 1&#160;10-5</p>
<p style="position:absolute;top:47px;left:420px;white-space:nowrap" class="ft01">PROGRAMMING WITH INTEL® STREAMING SIMD EXTENSIONS (INTEL® SSE)</p>
<p style="position:absolute;top:100px;left:69px;white-space:nowrap" class="ft02">•</p>
<p style="position:absolute;top:100px;left:95px;white-space:nowrap" class="ft03">Returns&#160;a zero&#160;result with&#160;the&#160;sign of the&#160;true result</p>
<p style="position:absolute;top:122px;left:69px;white-space:nowrap" class="ft02">•</p>
<p style="position:absolute;top:123px;left:95px;white-space:nowrap" class="ft03">Sets the&#160;precision&#160;and&#160;underflow exception&#160;flags</p>
<p style="position:absolute;top:147px;left:69px;white-space:nowrap" class="ft07">If&#160;the underflow exception is&#160;not masked,&#160;the&#160;flush-to-zero&#160;bit is&#160;ignored.<br/>The flush-to-zero mode is not compatible with IEEE&#160;Standard 754.&#160;The IEEE-mandated&#160;masked&#160;response to&#160;under-<br/>flow&#160;is&#160;to deliver&#160;the&#160;denormalized&#160;result (see<a href="o_7281d5ea06a5b67a-98.html">&#160;Section&#160;4.8.3.2,&#160;“Normalized&#160;and&#160;Denormalized&#160;Finite&#160;Numbers”).</a>&#160;<br/>The flush-to-zero mode&#160;is provided&#160;primarily&#160;for&#160;performance&#160;reasons. At&#160;the&#160;cost of a slight precision loss,&#160;faster&#160;<br/>execution&#160;can be achieved&#160;for&#160;applications where underflows are common&#160;and rounding&#160;the&#160;underflow&#160;result&#160;to&#160;<br/>zero&#160;can be tolerated.<br/>The&#160;flush-to-zero bit is&#160;cleared upon&#160;a power-up&#160;or&#160;reset&#160;of&#160;the processor,&#160;disabling&#160;the flush-to-zero mode.</p>
<p style="position:absolute;top:305px;left:69px;white-space:nowrap" class="ft04">10.2.3.4 &#160;&#160;Denormals-Are-Zeros</p>
<p style="position:absolute;top:334px;left:69px;white-space:nowrap" class="ft08">Bit 6 (DAZ) of the&#160;MXCSR register enables the&#160;denormals-are-zeros mode, which&#160;controls&#160;the&#160;processor’s response&#160;<br/>to&#160;a SIMD&#160;floating-point&#160;denormal operand&#160;condition. When the&#160;denormals-are-zeros flag is&#160;set,&#160;the processor&#160;<br/>converts all&#160;denormal source&#160;operands to&#160;a zero&#160;with&#160;the sign&#160;of&#160;the original operand before performing any&#160;<br/>computations on them.&#160;The&#160;processor&#160;does&#160;not set&#160;the denormal-operand exception flag (DE), regardless&#160;of the&#160;<br/>setting of&#160;the denormal-operand&#160;exception mask bit (DM);&#160;and it&#160;does&#160;not generate a&#160;denormal-operand exception&#160;<br/>if the&#160;exception is&#160;unmasked.<br/>The&#160;denormals-are-zeros&#160;mode&#160;is not compatible&#160;with&#160;IEEE&#160;Standa<a href="o_7281d5ea06a5b67a-98.html">rd 754 (see Section 4.8.3.2,&#160;“Normalized and&#160;<br/>Denormalized Finite&#160;Numbers”).</a>&#160;The denormals-are-zeros&#160;mode is provided&#160;to improve&#160;processor performance for&#160;<br/>applications&#160;such as&#160;streaming media processing, where rounding&#160;a denormal&#160;operand to&#160;zero does not appre-<br/>ciably affect&#160;the quality&#160;of the&#160;processed data.<br/>The denormals-are-zeros&#160;flag is&#160;cleared upon&#160;a&#160;power-up&#160;or reset of&#160;the processor,&#160;disabling&#160;the denormals-are-<br/>zeros mode.<br/>The&#160;denormals-are-zeros mode&#160;was&#160;introduced&#160;in&#160;the Pentium 4&#160;and Intel Xeon&#160;processor&#160;with&#160;the SSE2&#160;exten-<br/>sions; however,&#160;it is&#160;fully&#160;compatible&#160;with&#160;the SSE&#160;SIMD&#160;floating-point&#160;instructions&#160;(that is, the&#160;denormals-are-<br/>zeros&#160;flag affects&#160;the operation of the&#160;SSE SIMD floating-point instructions).&#160;In earlier IA-32&#160;processors and&#160;in&#160;<br/>some models of the&#160;Pentium&#160;4 processor,&#160;this flag&#160;(bit&#160;6)&#160;is reserved.&#160;S<a href="o_7281d5ea06a5b67a-274.html">ee Section 11.6.3, “Checking for the&#160;DAZ&#160;<br/>Flag in&#160;the MXCSR&#160;Register,”&#160;for&#160;</a>instructions&#160;for&#160;detecting the&#160;availability of this&#160;feature.<br/>Attempting&#160;to set bit&#160;6&#160;of&#160;the MXCSR&#160;register on&#160;processors that do not support the&#160;DAZ&#160;flag will&#160;cause a&#160;general-<br/>protection&#160;exception (#GP).&#160;See&#160;<a href="o_7281d5ea06a5b67a-275.html">Section 11.6.6,&#160;“Guidelines&#160;for Writing to&#160;the MXCSR Register,”&#160;for instru</a>ctions for&#160;<br/>preventing&#160;such general-protection exceptions by&#160;using the&#160;MXCSR_MASK&#160;value returned by the&#160;FXSAVE instruc-<br/>tion.</p>
<p style="position:absolute;top:744px;left:69px;white-space:nowrap" class="ft05">10.2.4&#160;</p>
<p style="position:absolute;top:744px;left:149px;white-space:nowrap" class="ft05">Compatibility of&#160;SSE Extensions&#160;with SSE2/SSE3/MMX and the x87 FPU</p>
<p style="position:absolute;top:775px;left:69px;white-space:nowrap" class="ft08">The&#160;state (XMM&#160;registers&#160;and&#160;MXCSR&#160;register) introduced&#160;into&#160;the IA-32 execution&#160;environment&#160;with&#160;the SSE&#160;<br/>extensions&#160;is shared with SSE2&#160;and SSE3&#160;extensions.&#160;SSE/SSE2/SSE3 instructions are&#160;fully&#160;compatible; they can&#160;<br/>be executed&#160;together&#160;in the&#160;same instruction stream&#160;with&#160;no&#160;need to&#160;save&#160;state when switching between&#160;instruc-<br/>tion sets.<br/>XMM&#160;registers&#160;are&#160;independent&#160;of the x87 FPU and MMX registers,&#160;so SSE/SSE2/SSE3 operations performed on the&#160;<br/>XMM registers can&#160;be performed&#160;in parallel with&#160;operations on the&#160;x87 FPU and MMX regist<a href="o_7281d5ea06a5b67a-275.html">ers (see Section 11.6.7,&#160;<br/>“Interaction of SSE/SSE2&#160;Instructions with x87&#160;FPU and&#160;MMX&#160;Instructions”).<br/></a>The&#160;FXSAVE and&#160;FXRSTOR instructions save&#160;and&#160;restore&#160;the SSE/SSE2/SSE3&#160;states&#160;along&#160;with the&#160;x87&#160;FPU and&#160;<br/>MMX state.</p>
<p style="position:absolute;top:977px;left:69px;white-space:nowrap" class="ft06">10.3&#160;</p>
<p style="position:absolute;top:977px;left:148px;white-space:nowrap" class="ft06">SSE DATA TYPES</p>
<p style="position:absolute;top:1013px;left:69px;white-space:nowrap" class="ft08">SSE extensions&#160;introduced&#160;one&#160;data&#160;type, the&#160;128-bit&#160;packed&#160;single-precision&#160;floating-point data type,&#160;to the&#160;IA-<br/><a href="o_7281d5ea06a5b67a-242.html">32 architecture (see Figure&#160;10-4). This data</a>&#160;type consists&#160;of&#160;four&#160;IEEE 32-bit single-precision floating-point values&#160;</p>
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