What is in the pipeline for when CMOS scaling comes to an end. Learn the basics to understand the future.This course offers a comprehensive, advanced state-of-the-art training program in the practice, fundamentals, and emerging trends of what there could be after CMOS More-Moore scaling comes to an end.

September 19-23.

What is in the pipeline for when CMOS scaling comes to an end? Learn the basics to understand the future.

Who should attend

The course is in the first place intended for PhD students who want to get an in depth education in the basics of CMOS technology, process development and logic and memory device design. But the course will also have special appeal to those engineers, supervisors, managers and directors working in, or having responsibility for process development, field process support, process integration, logic and memory device design, chip manufacturing, materials for IC processing, and process and metrology tool development and support. For those new to the field, the course offers a rapid, yet, in-depth exposure to the ULSI circuit processing cycle. More experienced participants will benefit from the timely update describing the tradeoffs associated with the emerging technologies. Familiarity with wafer fabrication is also vital to circuit designers. Since design decisions are influenced by processing limitations those designers possessing knowledge will be more capable of performing the trade-offs between performance and yield. Designers working for a fabless semiconductor company will also be more effective when interfacing with their silicon foundry, if they have a foundation in silicon processing.