Improved Analytical Delay Models for RC-Coupled Interconnects
Feng Shi
Xuebin~Wu
and Zhiyuan~Yan \thanks{Feng Shi
Xuebin Wu
and Zhiyuan Yan are with the Department of ECE
PA 18015
As the process technologies scale into deep submicron region, crosstalk delay is becoming increasingly severe, especially for global on-chip buses. To cope with this problem, accurate delay models of coupled interconnects are needed. In particular, delay models based on analytical approaches are desirable, because they not only are largely transparent to technology, but also explicitly establish the connections between delays of coupled interconnects and transition patterns, thereby enabling crosstalk alleviating techniques such as crosstalk avoidance codes (CACs). Unfortunately, existing analytical delay models, such as the widely cited model in~\cite{Sot01}, have limited accuracy and do not account for loading capacitance. In this paper, we propose analytical delay models for coupled interconnects that address these disadvantages. By accounting for more wires and eschewing the Elmore delay, our delay models achieve better accuracy than the model in \cite{Sot01}. %The model in \cite{Sot01} assumes simultaneous transitions on all wires. This assumption is unrealistic in many scenarios and hence results in diminished effectiveness of CACs. Hence, our delay models are refined to account for asynchronous switching instants. They not only analyze the delays of coupled interconnects with synchronization problems, but also provide new guidelines to the design of CACs.
Delay_model_Brief_Apr2.tex
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\begin{document}
\title{Improved Analytical Delay Models for RC-Coupled Interconnects}

\author{Feng Shi, Xuebin~Wu, and Zhiyuan~Yan

  \thanks{Feng Shi, Xuebin Wu, and Zhiyuan
    Yan are with the Department of ECE,
    Lehigh University, PA 18015, USA. E-mails:\{fes209, xuw207,
     yan\}@lehigh.edu.}}

%  \thanks{Ying Wang is with Qualcomm Flarion
%    Technologies, Bridgewater, NJ 08807, USA. E-mail:
%    aywang11@gmail.com.}}



%%\documentclass[11pt,onecolumn,draftcls]{IEEEtran}
%\documentclass[10pt,journal]{IEEEtran}
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%\usepackage{verbatim}
%\usepackage{multirow}
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%\usepackage{algorithm2e}
%
%
%\title{Composite Cyclotomic Fourier Transforms \\with Reduced
%  Complexities}
%
%\author{Xuebin~Wu, Meghanad~Wagh, Ning~Chen, Zhiyuan~Yan, and Ying~Wang
%
%  \thanks{Xuebin Wu, Meghanad Wagh, Ning Chen, and Zhiyuan
%    Yan are with the department of ECE,
%    Lehigh University, PA 18015, USA. E-mails:\{xuw207, mdw0, nic6,
%     yan\}@lehigh.edu.}
%
%  \thanks{Ying Wang is with Qualcomm Flarion
%    Technologies, Bridgewater, NJ 08807, USA. E-mail:
%    aywang11@gmail.com.}}




\maketitle
\begin{abstract}
As the process technologies scale into deep submicron region, crosstalk delay is becoming increasingly severe, especially for global on-chip buses. To cope with this problem, accurate delay models of coupled interconnects are needed.
In particular, delay models based on analytical approaches are desirable, because they not only are largely transparent to technology, but also explicitly establish the connections between delays of coupled interconnects and transition patterns, thereby enabling crosstalk alleviating techniques such as crosstalk avoidance codes (CACs).
Unfortunately, existing analytical delay models, such as the widely cited model in~\cite{Sot01}, have limited accuracy and do not account for loading capacitance. In this paper, we propose analytical delay models for coupled interconnects that address these disadvantages.
By accounting for more wires and eschewing the Elmore delay, our delay models achieve better accuracy than the model in \cite{Sot01}.
%The model in \cite{Sot01} assumes simultaneous transitions on all wires. This assumption is unrealistic in many scenarios and hence results in diminished effectiveness of CACs. Hence, our delay models are refined to account for asynchronous switching instants. They not only analyze the delays of coupled interconnects with synchronization problems, but also provide new guidelines to the design of CACs.
\end{abstract}
%
\begin{keywords}
Crosstalk, interconnect, delay, bus
\end{keywords}
%

\section{Introduction}
\label{sec:intro}
Crosstalk caused by coupling capacitance between adjacent wires leads to additional delay to multi-wire buses. As the process technologies scale into deep submicron region,
coupling capacitance between adjacent wires and hence crosstalk delays increase greatly. According to the International Technology Roadmap
of Semiconductors (ITRS) \cite{ITRS}, gate delay \textbf{decreases} with scaling, while
global wire delay \textbf{increases}. Hence, the crosstalk delay problem is becoming increasingly severe in VLSI designs, especially for global on-chip buses, and will become the performance bottleneck in many high-performance VLSI designs.

This paper focuses on analytical delay models applicable to general coupled interconnects. Although various delay models of interconnects have been proposed in the literature (see, for example, \cite{Kay98,Pil98,Alp01,Sot01,Sot02,Liu02,Dav002,Abo02,Tu06,Mol09}), few are comparable to our work in this paper. Some delay models (see, for example, \cite{Kay98,Alp01,Liu02,Mol09,Pil98,Abo02}) do not consider crosstalk from adjacent wires. Furthermore, most previously proposed delay models are based on numerical approaches (see, e.g., \cite{Kay98,Alp01,Liu02,Dav002,Tu06,Mol09,Pil98,Abo02}). They can achieve high accuracy, but they have several drawbacks. First, they sometimes lead to lookup tables of delays from any initial state to any next state (see, for example, \cite{Mol09}), which are often bulky and difficult to obtain and use. Second, numerical approaches in \cite{Kay98,Pil98,Alp01,Liu02,Abo02} are technology-dependent and their delays often depend on many parameters. Hence these approaches have poor portability and are not applicable to general cases. Third, the delays obtained by the numerical approach offer little insight, and are not conducive to technology-independent crosstalk alleviation techniques such as crosstalk avoidance codes (CACs) (see, for example, \cite{Dua01,Vic01,Sri07,Wu09}). Fourth, numerical approaches often have very high complexities. In contrast, analytical approaches are advantageous in these aspects. Analytical approaches depend on few technology parameters, and hence they are largely technology independent. Furthermore, analytical approaches illustrate the connection between delays of coupled interconnects and transition patterns, thus enabling us to design CACs. Finally, analytical approaches have very low computational complexities.
A widely cited analytical delay model proposed by Sotiriadis \emph{et al.} \cite{Sot01,Sot02}, which uses the similar methodology to that in \cite{SC_TVLSI02}, appears to be the most comparable previous delay model to our work in this paper.


%To calculate the interconnect delay, people have proposed several approaches, which could be divided into two types: analytical way and experimental way. The experimental method, which is based on the simulation, has higher accuracy, such as table lookup method \cite{Mol09}. However, this method is technology dependent and affected by more parameters of the technology. For the table lookup method, it is difficult to get and use the bulky tables to give the delay from any initial state to next state. The analytical method is more preferable. It can give simple models for the delay. Since the analytical method treats the arbitrary patterns with fewer cases, it is easy to give the delay for any transition. The delay model by analytical method is abstract. It has fewer parameters in its expression which is easy to get for different technologies. For CACs design, the analytical method is much better.

Based on the model in \cite{Sot01,Sot02}, the delay of the $k$-th wire ($k \in \left\{1,2,\cdots,m \right\}$) of an $m$-bit bus is given by
\begin{equation}
  T_k = \left\{
    \begin{array}{ll}
      \tau_0[(1+\lambda)\Delta_1^2-\lambda\Delta_1\Delta_2], & k=1\\
      \tau_0[(1+2\lambda)\Delta_k^2-\lambda\Delta_k(\Delta_{k-1}+\Delta_{k+1})],
      & k\neq 1,m\\
      \tau_0[(1+\lambda)\Delta_m^2-\lambda\Delta_m\Delta_{m-1}],& k=m,\\
    \end{array}
  \right.
  \label{Eq:1}
\end{equation}
%\begin{equation}
%T_k = \left\{ \begin{array}{ll}
%[(1+\lambda)\Delta^2_1-\lambda \Delta_1 \Delta_2]\tau_0 & k=1\\
%[(1+2\lambda)\Delta^2_k-\lambda \Delta_k(\Delta_{k-1}+\Delta_{k+1})]\tau_0 & k \neq 1,m \\
%[(1+\lambda)\Delta^2_m-\lambda \Delta_m \Delta_{m-1}]\tau_0 & k=m
%\end{array} \right.
%\label{Eq:1}
%\end{equation}
where $\lambda$ is the ratio of the coupling capacitance between
adjacent wires and the ground capacitance of each wire,
%between the $k$-th wire and the ground,
$\tau_0$ is the intrinsic delay of a transition on a single wire,
and $\Delta_k$ is $1$ for $0\rightarrow 1$ transition, $\textnormal{-}1$ for
$1\rightarrow 0$ transition, or $0$ for no transition on the $k$-th
wire. We observe that in this model, the delay of the $k$-th wire
depends on the transition patterns of wires $k-1$, $k$, and $k+1$ only. Since all possible values of $T_k$ in Eq.~(\ref{Eq:1}) are $(1+i\lambda)\tau_0$ for $i \in \{0,1,2,3,4\}$, all transition patterns on wires $k-1$, $k$, and $k+1$ can be divided into five classes according to their corresponding $i$. These five classes are denoted as $iC$ for $i \in \{0,1,2,3,4\}$ (this classification was also used in \cite{Dua01}). Based on this model, various CACs (see, for example,  \cite{Dua01,Vic01,Sri07,Wu09}) have been proposed, based on the central idea of achieving a reduced delay by limiting transition patterns over the bus, at the expense of additional wires.


However, the model in \cite{Sot01} have two significant drawbacks. First, the model in \cite{Sot01} has limited accuracy. In a bus with more than three wires, the simulated wire delay for $0C$ transition patterns is much larger than $\tau_0$, the delay of $0C$ given by (\ref{Eq:1}). This implies that the scheme that uses two shield wires with the same transition to achieve a delay of $\tau_0$ (see, for example, \cite{Dua04}) will be ineffective. Our simulation results also show that the delays of other classes of transition patterns given by Eq.~(\ref{Eq:1}) have limited accuracy as well. This is partially because of the model's dependence on only three wires.
%This is partially because of the model's simplicity, observed above.
Also, the model in \cite{Sot01} uses in its derivation the Elmore delay, which tends to overestimate the delay \cite{Elm48,Gup97}.
%Furthermore, the delay depends on the transitions of its adjacent two wires only.

The second drawback of the model in \cite{Sot01} is that it does not account for the loading capacitance. It has been shown that the loading capacitance is crucial in real practice and can affect the total delay for all patterns.
%But the classification of all transition patterns would not change.

%The third drawback of the model in \cite{Sot01} is that it assumes simultaneous transitions on all the wires, and hence does not work for buses with synchronization problems. However, for global buses where buffer insertion techniques are usually used to reduce their delay \cite{Tsa06}, simultaneous signal transitions on the bus cannot be guaranteed. An on-chip bus with buffer insertion is  shown in  Fig.~\ref{fig:buf}, where {\it Cc} denotes the coupling capacitance between wires and {\it Cg} the sum of capacitance to the ground and the gates of the buffers. Due to different transition patterns on the bus, the delays at the inputs of the buffers are not always the same, and hence the restored signals at the outputs of buffers are not synchronized. For instance, the skew between different outputs can be as large as 500 ps for high-speed repeaters~\cite{Giga}.
%\begin{figure}[!tb]
%\begin{minipage}[b]{1.0\linewidth}
%  \centering
% \centerline{\epsfig{figure=bufferinsertion,width=8.5cm}}
%\end{minipage}
%\caption{Schematic of the on-chip bus with buffer insertion.}
%\label{fig:buf}
%\end{figure}

%The accuracy of the model in \cite{Sot01} is vulnerable to the synchronization of the switching instants of all wires in a bus. Consequently, the effectiveness of CACs designed based on the model in \cite{Sot01} severely diminishes in the presence of the synchronization problems. In \cite{Dua04}, it was shown that CACs designed to achieve a delay of $\tau_0$ without synchronization problems were susceptible to skew. When the skew on the outer shielding wire is sufficiently large, the actual delay of the center wire is close to $(1+2\lambda)\tau_0$, much greater than $\tau_0$ for large $\lambda$ \cite{Dua04}.


Addressing these disadvantages for the model in \cite{Sot01}, in this paper we propose analytical delay models for coupled interconnects. Our delay models first derive closed-form expressions of the signals on the bus via a distributed RC model, and then approximate the wire delays by evaluating these closed-form expressions.
Our delay models differ from the model in \cite{Sot01} in three aspects. First, in our delay models, we eschew the Elmore delay used in the model in \cite{Sot01}. Then, we consider either three wires or five wires in our delay models for improved accuracy. Due to these two differences, our models have significantly improved accuracy than the model in \cite{Sot01}. Finally, we take into account the buffer effects (driver resistance and loading capacitance). Our delay models also maintain the simplicity of the model in \cite{Sot01}, and the transition patterns are divided into several categories based on their delays. Hence, our delay models are easy to use and conducive to the design of CACs.
Although our delay models consider adjacent three and five wires in this paper, our models are applicable to buses of any number of wires.

Simulation results show that our delay models offer significant advantages than the model in \cite{Sot01}. Our simulations results fall into three scenarios. First, we compare the delays produced by our model and the model in \cite{Sot01} with the simulated delays for three- or five-wire buses. This is motivated by partial coding schemes (see, e.g., \cite{Dua01}, \cite{Vic01}, and \cite{Sri07}), which divide a wide bus into sub-buses with a few wires and separate them by shielding wires.
Second, we obtain extensive simulation results for 17- and 33-wire buses assuming arbitrary transition patterns. Third, we assume the transition patterns are limited to those of CACs. In all three scenarios, our five-wire delay model is much more accurate than the model in \cite{Sot01}. 


With the scaling of technologies, the inductance is becoming significant and impacts the signals on the bus greatly. Due to the coupling effect of inductance, the worst-case patterns for an RLC modeled bus are quite different from that of an RC modeled bus~\cite{Tu06}. Hence, the CAC design methodology would change greatly due to the inductance effect.
However, our delay models do not consider the inductance effect  for two reasons.
First, it seems difficult to derive a closed-form expression of the signals on the bus based on the RLC model. Hence, our methodology cannot be easily adapted from the distributed RC model to an RLC model. Second, according to the criteria in \cite{Ism99}, the inductance effect is significant in some cases, but are negligible in other cases. Specifically, the range of significance of the inductance effect is given by $\frac{t_r}{2\sqrt{lc}}<x<\frac{2}{r}\sqrt{\frac{l}{c}}$ \cite{Ism99}, where $x$ is the length of the wire, $t_r$ the input transition time, and $r$, $l$, and $c$ the resistance, inductance, and capacitance per unit length, respectively.
%If $l$ is out of the range, or the range is non-existent, the inductance effect is negligible.
According to \cite{CSLJ_JLPE08}, the inductance effect is not negligible for very deep submicron technologies and extremely long wires.
In current industry applications, the on-chip inductance effect is still insignificant. This conclusion was also confirmed by other works: the 16-bit, 32Gb/s, 5mm-long bus and 8-bit, 16Gb/s, 10mm-long bus in \cite{Zha09} show that the distributed RC model is sufficiently accurate for these high-speed long interconnects. In our work, our delay models are derived based on 5mm-long buses under a 45nm technology, where inductance effect is negligible.
%Hence, our delay models are suitable when the inductance effect is negligible.

%Also, although  our delay models in this paper do not account for the buffer effects, they can be readily modified to account for both using the techniques in \cite{Sak93}. In general, driver resistance and loading capacitance tend to increase the delay.

%
%
%The criteria to characterize the importance of inductance was proposed in \cite{Ism99}. It demonstrates that a range of the length of interconnect exists in which case the inductance effects are significant. For some cases, the inductance effects are negligible despite the length of the interconnect \cite{Ism99}. A 16-b, 32-Gb/s, 5-mm-long bus and an 8-b, 16-Gb/s, 10-mm-long bus were presented in \cite{Zha09}. It shows the RC model are still good for these long interconnects. So we focus on the buses where inductive effects are not significant and propose improved interconnect delay models based on the distributed RC model.






%are not limited to buses of only 3 and 5 wires for several reasons. First, some  In this case, our 3-wire and 5-wire delay models provide more accurate delay analysis of the sub-buses than the model in \cite{Sot01}. Second, even when the bus has more than five wires, our 5-wire delay model is still more accurate than the model in \cite{Sot01}. To verify the accuracy of our 5-wire model, we also give simulation results of 17-wire and 33-wire buses. The results show that the delays by our 5-wire model are accurate for both cases. So for buses of only small number of wires, our 3-wire and 5-wire models are accurate. For buses with more than 5 wires, we can also approximate the delays better than the model in \cite{Sot01}.

%(2) Even if we expand our delay model, which focuses on a bus with smaller width, to a general bus with more wires, simulated results show the error of our approximate delay is very small. And the delay by our model is much below that by \cite{Sot02}, which usually gives upper delay bounds.
%
%(3) In order to improve the accuracy of our model, we plan to include more wires to our model.

%We first present a 3-wire model based on the lumped RC model. Then we give the close-form expressions using linear superpositions. By evaluating these expressions, we give the delays  of different transition patterns. Compared with that in \cite{Sot02}, our 3-wire model has accurate delays for all kinds of transition patterns on the 3-wire bus. Furthermore, we introduce a 5-wire model and approximate the delays of different transition patterns using similar method. Our model could approximate the delay of all transition patterns better, including the delay of $0C$ case, which is inaccurate based on the model in \cite{Sot01}. Finally we expand our 3-wire model and 5-wire model to patterns with synchronization problems. The delays are given in line with the time differences between the middle wire and its neighboring wires. The simulation results show that it works well for 3-wire bus and 5-wire bus with synchronization problems.

%Also, our delay models in this paper are modified to account for the buffer effects using the techniques in \cite{Sak93}. In general, including the buffer effect tends to increase the delay.



The rest of the paper is organized as follows. In Section~\ref{sec:model}, we propose our delay models. The delay models are also modified to account for the buffer effects.
%for 3-wire and  5-wire buses, we first introduce the lumped RC model of the bus, then derived closed-form expressions of signals on the bus, and finally analyze their delays.
In Section~\ref{sec:simulation}, we present extensive simulation results for our delay models. Concluding remarks are provided in Section~\ref{sec:conclusion}.
%The buffer effect is assumed to be negligible in Section~\ref{sec:model}. In the appendix, the delay models in Section~\ref{sec:model} are modified to account for the buffer effect.

\section{Delay model}
\label{sec:model}

In this section, we first present the system model, where switching instants of all wires in the bus are assumed simultaneous. For three-wire and five-wire buses, we then derive closed-form expressions for outputs of the bus, and finally approximate their delays and compare them with those by the model in \cite{Sot01}.

\subsection{System model}
%Although on-chip buses are often modeled by the distributed RC model~\cite{Rab96}, which provides a more accurate model of a bus, we  do not consider the distributed RC model in this paper, since it is not suitable for analytic modeling of wires. Instead, the lumped RC model \cite{Rab96} is used in this paper for two reasons. First, it is conducive to analytic modeling of wires. Second, it has been suggested that the delay based on the lumped RC model is greater than that based on the distributed RC model \cite{Pum03}. Since we are interested in analytically deriving the worst-case delays of the bus, the lumped RC model is suitable for this purpose.

In this paper, we focus on global interconnects connecting different modules for communication, such as data and address buses, and use the distributed RC model for interconnect modeling. For simplicity, we assume regular interconnects, which have uniformly distributed parameters and are paralleled routed in the same metal layer without turnings. Hence, the interconnects are modeled as transmission lines, which can be characterized by the telegrapher's equations.
For complex interconnect structures with jumps and turnings, additional resistance due to vias and unequal length of wires should be included, which makes the interconnect behavior more complicated. However, crosstalk delays are expected to increase due to the additional resistance.
The partially coupled buses are more complex and hence are not considered in this paper. We plan to investigate this in our future work.
%we focus on on-chip buses that are routed parallel and coplanar.
The capacitance between non-adjacent wires is negligible compared with capacitance between adjacent wires, since the capacitive coupling effect is a short range effect~\cite{SC_TVLSI02}.
The distributed RC model is often used to approximate the buses~\cite{Rab96}. Although the closed-form expressions of the signals on the bus via a distributed RC model are sums of infinite terms, usually sums of the two most significant terms provide a very close approximation of signals on the bus \cite{Sak93}.

%which provides a more accurate model of a bus. Although the closed-form expressions given by the distributed model have infinite sums \cite{Dav001,Dav002}, it shows that keeping the first two terms are accurate enough for the delay approximations. So, the distributed RC model is suitable for analytic modeling of wires. Since we are interested in analytically deriving the worst-case delays of the bus, the distributed RC model is suitable for this purpose.

The distributed RC model of an $m$-wire bus is shown in Fig.~\ref{fig:3bus}, where $V_i(x,t)$ denotes the transient signal at a position $x$ along wire $i$ for $i \in \{1,2,\cdots,m\}$, $r$ and $c$ denote the resistance and capacitance per unit length, respectively. Also, $\lambda_c$ denotes the coupling capacitance per unit length between two adjacent wires. The output resistance of a driver is approximated as a linear resistor, $R_S$, and the loading due to a receiver is modeled as a capacitance, $C_L$. In this work, we focus on a uniformly distributed bus and hence assume the parameters $r$, $c$, and $\lambda$ are the same for all the wires.

\begin{figure}[!tb]
\begin{minipage}[b]{1.0\linewidth}
  \centering
 \centerline{\epsfig{figure=mwirerc,width=8.5cm}}
\end{minipage}
\caption{A distributed RC model of an $m$-wire bus.}
\label{fig:3bus}
\end{figure}


We use the 50\% delay, which is defined as the time difference between the respective instants when the input signal and corresponding output signal cross 50\% of the supply voltage $V_{dd}$. According to \cite{Kah99}, the delays of global interconnects are slightly affected by the slew rate. Since this work focuses on global interconnects, we ignore input slew and assume ideal step signals are applied on the bus directly. In this paper, we use the same classification $iC$ for $i=0,1,2,3,4$ in \cite{Sot01} and focus on the worst 50\% delay of any wire for all classes to formulate our delay models.
We consider the closest neighbors for crosstalk, since farther wires have weaker coupling effects.
%To account for most adjacent two wires (one wire to the left and one to the right), we consider a 3-wire pattern and derive the delay of the middle wire. To account for most adjacent four wires (two wires to the left and two to the right), we consider a 5-wire pattern and derive the delay of the middle wire. For boundary wires, we derive the delay separately, since some of the coupling wires are missing.
In Section~\ref{sec:3m}, we first focus on internal wire, wire 2 in a three-wire model, to account for most adjacent two wires (one wire to the left and one to the right). In Section~\ref{sec:5w}, we focus on internal wire, wire 3 in a five-wire model, to account for most adjacent four wires (two wires to the left and two to the right).
In Section~\ref{sec:boundary}, we derive the delay for boundary wires, wires 1, 2, 4, and 5 in a five-wire model.
In Section~\ref{sec:application}, we show how to identify the worst-case delays among all wires for a wide bus via a shift window scheme.
%For some transition patterns, the delay of the middle wire(s) is the greatest among all wires. For other transition patterns, other wires may have a greater delay, but the worst delays of all wires corresponding to the same class are close.

%Since all wires of the bus are usually of the same length, we assume $R_i=R$ and $C_i=C$ for $i \in \{1,2,\cdots, m\}$ and $C_{i,i+1}=\lambda C$ for $i \in \{1,2,\cdots, m-1\}$.
%Since all wires of the bus are usually of the same length, we assume $r$, $c$, and $\lambda$ are the same for all wires of the bus.

%The delay caused by the buffer is often relatively small in comparison to the crosstalk delay due to the large coupling effect in DSM technology. Hence, the effect of buffer is considered negligible.
In this section, we first derive delay models by assuming that the buffer effects (driver resistance and loading capacitance) are negligible. This is an important case since the propagation delay is characterized only by the distributed interconnects. Then, in Section~\ref{sec:revised}, we modify the delay models to account for the buffer effects, which are crucial in real practice. It has been shown that the buffer effects would increase the total delay for all patterns.
%But the classification of all transition patterns would not change.


Below we first investigate the case $m=3$ and then extend our results to the case $m=5$. There are two reasons for studying the three-wire model. First and foremost, the derivation of our five-wire model is based on the three-wire model. Second, our three-wire model is more accurate than our five-wire model for buses with only three wires, which is of interest for partial coding schemes (see, e.g., \cite{Dua01}, \cite{Vic01}, and \cite{Sri07}).
%Then, we modify our models accordingly with consideration of the buffer effect. In this case, only the boundary conditions need to be changed. The signal expressions under revised boundary conditions are still sums of infinite terms~\cite{Dav002}.
%Generally, source resistance and load capacitance tend to increase the delay.
%For simplicity, we assume $m$ is odd, and hence wire $\frac{m+1}{2}$ is the middle wire.
We use $T^{iC}_m$ to denote the worst delay of the middle wire (wire $\frac{m+1}{2}$) of an $m$-wire bus for all $iC$ patterns.

\subsection{Internal wires for three-wire model}
\label{sec:3m}
%Usually, the effects of drivers and receivers are insignificant due to the comparatively small driver resistance and loading capacitance.

In~\cite{Sak93}, the crosstalk of two coupled lines was described by partial differential equations (PDEs), and a technique for decoupling these highly coupled PDEs was introduced by using eigenvalues and corresponding eigenvectors.
Using the same technique as in \cite{Sak93}, we obtain the differential equations describing a three-wire bus with length $L$:
%\begin{equation}
%\frac{\partial^2}{\partial x^2}\left[\begin{array}{c} V_1(x,t) \\ V_2(x,t) \\ V_3(x,t) \end{array}\right]
%=RC\frac{\partial}{\partial t}\left[\begin{array}{c} V_1(x,t) \\ V_2(x,t) \\ V_3(x,t) \end{array}\right]
%\label{Eq:2}
%\end{equation}
\begin{equation}
\frac{\partial^2}{\partial x^2}\mathbf{V}(x,t)
=\mathbf{RC}\frac{\partial}{\partial t}\mathbf{V}(x,t),
\label{Eq:2}
\end{equation}
where $\mathbf{V}(x,t)=[V_1(x,t)\;V_2(x,t)\;V_3(x,t)]^T$ and $V_i(x,t)$ denotes the voltage of wire $i$ at distance $x$ ($0\le x \le L$) at time $t$ for $i=1,2,3$,
$\mathbf{R}=\mbox{diag}\{r \; r \; r\}$, and $\mathbf{C}=c\left[ \begin{array}{ccc} 1+\lambda & -\lambda & 0 \\ -\lambda & 1+2\lambda & -\lambda\\
0 & -\lambda & 1+\lambda \end{array}\right]$.


The boundary conditions are given by
\begin{equation*}
\left\{ \begin{array}{l}
V_i(0,t)=V_i^p-(V_i^p-V_i^f) u(t) \\
I_i(L,t)=0
\end{array} \mbox{ for } i=1,2,3 \right.
\end{equation*}
where $V^p_i$ and $V^f_i$ denote the initial and final voltages of the transition on wire $i$, respectively.
%Since all loading (or coupling) capacitors are the same, the solutions to (\ref{Eq:2}) are of the form $V_{i}(t)=K_{i1}+K_{i2} e^{-t/a}+K_{i3} e^{-t/b}$, for $i \in\{1,2,3\}$, where $K_{ij}\, (1\le i,j \le 3)$ denotes coefficient to the $j$-th term of the expression on the $i$-th wire.

%\[
%det\left[ \begin{array}{ccc} c+\lambda c -p & -\lambda c & 0 \\ -\lambda c & c+2\lambda c -p & -\lambda c \\
%0 & -\lambda c & c+\lambda c -p \end{array}\right]=0;
%\]

We find the three eigenvalues of $\mathbf{C}/c$, $p_1=1$, $p_2=(1+\lambda)$, and $p_3=(1+3\lambda)$, and their corresponding eigenvectors $\mathbf{e}_i$'s, $[1 \, 1 \, 1]^T$, $[1 \, 0 \, \textnormal{-}1]^T$, and $[\textnormal{-}1 \, 2 \, \textnormal{-}1]^T$, respectively. Hence, Eq.~(\ref{Eq:2}) is transformed to
\begin{equation}
\frac{\partial^2}{\partial x^2}U_i(x,t)=rcp_i\frac{\partial}{\partial t} U_i(x,t) \mbox{ for }i=1,2,3,\label{Eq2}
\end{equation}
where $U_i(x,t)=\mathbf{V}^T(x,t) \mathbf{e}_i$ for $i=1,2,3$. So $U_1(x,t)=V_1(x,t)+ V_2(x,t) + V_3(x,t)$, $U_2(x,t)=V_1(x,t)-V_3(x,t)$, and $U_3(x,t)=2V_2(x,t)-V_1(x,t)-V_3(x,t)$.

Applying Laplace transform on both sides of Eq.~(\ref{Eq2}), we have
\begin{equation}
\frac{\partial^2}{\partial x^2}U_i(x,s)=rcp_i[s U_i(x,s) - U_i(x,0)] \mbox{ for }i=1,2,3. \label{Eq1}
\end{equation}

Using appropriate initial conditions, we solve Eq.~(\ref{Eq1}) for $U_i(x,t)$ and obtain $V_2(L,t)=\frac{1}{3}[U_1(L,t)+U_3(L,t)]$.
By solving $V_2(L,t)=0.5V_{dd}$, we can approximate the 50\% delay of a three-wire bus for different transition patterns.


In this paper, we use ``$\uparrow$" to denote a transition from 0 to the supply voltage $V_{dd}$ (normalized to 1), ``-" no transition, and ``$\downarrow$" a transition from $V_{dd}$ to 0.

For $0C$ pattern $\u\u\u$, the output of wire 2 is given by~\cite{Sak93} $V_2(L,t)=1 + \sum\limits^\infty_{n=1}\frac{(\textnormal{-}1)^n}{\frac{\pi}{4}(2n-1)} e^{-\frac{t}{\tau}(2n-1)^2}$, where $\tau_0=\frac{rcL^2}{2}$, and $\tau=\frac{8}{\pi^2}\tau_0$.
%\label{Eq:inf}

For the 50\% delay, keeping only the first exponential term is accurate enough. So we have $V_2(L,t)\doteq 1- \frac{4}{\pi}e^{-\frac{t}{\tau}}$.
Similarly, we keep only the first exponential term as the solution for other cases.
Solving $V_2(L,t)=0.5$, we have $T^{0C}_3\doteq\left(\ln{\frac{8}{\pi}}\right)\tau$.
Similarly, the closed-form expressions of wire 2 and approximate delays for other classes are derived and summarized in Table~\ref{tab:3wire}, where $T^{iC}_3$ the approximate delay for $iC$ pattern by our three-wire model.

\begin{table}[!thb]
\caption{Closed-form expressions of signal on wire 2 and approximate delays in a three-wire bus ($V_2(L,t) = 1-A_1 e^{-\frac{t}{\tau}} - A_2 e^{-\frac{t}{(1+3\lambda)\tau}}$, $\tau_0=\frac{rcL^2}{2}$, and $\tau=\frac{8}{\pi^2}\tau_0$.)}\label{tab:3wire}
\begin{center}
\begin{tabular}{|c|c|c|c|c|}
\hline
\multirow{2}{*}{$iC$} & Worst & \multicolumn{2}{|c|}{Coeffs. of $V_2(L,t)$} & \multirow{2}{*}{$T_3^{iC}$}\\
\cline{3-4}
& Pattern & $A_1$ & $A_2$ & \\
\hline
$0C$ & $\u\u\u$ & $\frac{4}{\pi}$ & 0 & $\left(\ln{\frac{8}{\pi}}\right)\tau$ \\
\hline
$1C$ & $\u\u$- & $\frac{8}{3\pi}$ & $\frac{4}{3\pi}$ & $\left(\ln{\frac{16}{\pi}}\right)\tau$\\
\hline
$2C$ & -$\u$- & $\frac{4}{3\pi}$ & $\frac{8}{3\pi}$ & $\left(\ln{\frac{16}{3\pi}}\right)(1+3\lambda)\tau$ \\
\hline
$3C$ & $\d\u$- & 0 & $\frac{4}{\pi}$ & $\left(\ln{\frac{8}{\pi}}\right)(1+3\lambda)\tau$ \\
\hline
%$4C$ & $\d\u\d$ & $-4/(3\pi)$ & $16/(3\pi)$ & $\left(\ln{\frac{32}{3\pi}}\right)(1+3\lambda)\tau$ \\
$4C$ & $\d\u\d$ & $\textnormal{-}\frac{4}{3\pi}$ & $\frac{16}{3\pi}$ & $\left(\ln{\frac{32}{3\pi}}\right)(1+3\lambda)\tau$ \\
\hline
\end{tabular}
\end{center}
\end{table}


%\begin{enumerate}
%\item $0C$ class:
%
%%For the $0C$ pattern such as $\uparrow \uparrow \uparrow$, the output of wire 2 is given by $V_2(t)=1 - e^{-\frac{t}{\tau_0}}$. Assuming $V_2(t)=0.5$, we have
%%\[T^{0C}_3\doteq(\ln 2)\tau_0.\]
%
%It can be shown that the worst-case pattern for $0C$ is $\uparrow \uparrow \uparrow$. For this pattern, the boundary conditions of voltages are given by
%\[
%U_1(0,t)=3u(t), \quad U_3(0,t)=0,
%\]
%
%Due to the assumption of zero load capacitance, the boundary conditions of currents are given by
%\[
%-\frac{\partial U_i(L,t)}{\partial x}R^{-1}=0 \mbox{ for } i=1,3.
%\]
%
%Since there is no crosstalk between wire 1 (or 3) and wire 2, we can use the result of \cite{Dav002} directly, and the output of wire 2 is given by
%\begin{equation}
%V_2(L,t)=1 + \sum\limits^\infty_{n=1}\frac{(-1)^n}{\frac{\pi}{4}(2n-1)} e^{-\frac{t}{\tau}(2n-1)^2},
%\label{Eqinf}
%\end{equation}
%where $\tau_0=\frac{rcL^2}{2}$ and $\tau=\frac{8}{\pi^2}\tau_0$.
%
%
%For the 50\% delay, keeping only the first exponential term in Eq.~(\ref{Eqinf}) is accurate enough. So we have
%\begin{equation}
%V_2(L,t)\doteq 1- \frac{4}{\pi}e^{-\frac{t}{\tau}}.
%\label{Eqappr}
%\end{equation}
%%Similarly, we keep only the first exponential term as the solution for other cases.
%
%Solving $V_2(L,t)=0.5$ in Eq.~(\ref{Eqappr}), we have
%\[T^{0C}_3\doteq\left(\ln{\frac{8}{\pi}}\right)\tau.\]
%
%\item $1C$ class:
%
%
%
%The worst-case for $1C$ is $\uparrow \uparrow$-. For this pattern, the output of wire 2 is approximated by
%\[
%V_2(L,t)  \doteq 1-\frac{8}{3\pi}e^{-\frac{t}{\tau}} - \frac{4}{3\pi}e^{-\frac{t}{(1+3\lambda)\tau}}.
%\]
%
%The 50\% delay of wire 2 is approximated by
%\[
%T^{1C}_3\doteq\left(\ln{\frac{16}{\pi}}\right)\tau.
%\]
%
%\item $2C$ class:
%
%
%
%The worst-case for $2C$ is -$\uparrow$-. For this pattern, the output of wire 2 is approximated by
%\[
%V_2(L,t) \doteq 1-\frac{4}{3\pi}e^{-\frac{t}{\tau}} - \frac{8}{3\pi}e^{-\frac{t}{(1+3\lambda)\tau}}.
%\]
%
%The 50\% delay of wire 2 is approximated by
%\[
%T^{2C}_3\doteq\left(\ln{\frac{16}{3\pi}}\right)(1+3\lambda)\tau.
%\]
%
%
%\item $3C$ class:
%
%
%The worst-case for $3C$ is $\downarrow \uparrow$-. For this pattern, the output of wire 2 is approximated by
%\[
%V_2(L,t) \doteq 1 - \frac{4}{\pi}e^{-\frac{t}{(1+3\lambda)\tau}}.
%\]
%
%The 50\% delay of wire 2 is approximated by
%\[
%T^{3C}_3\doteq\left(\ln{\frac{8}{\pi}}\right)(1+3\lambda)\tau.
%\]
%
%\item $4C$ class:
%
%It can be shown that the worst-case for $4C$ is $\downarrow \uparrow \downarrow$. The output of wire 2 is approximated by
%\[
%V_2(L,t) \doteq 1+\frac{4}{3\pi}e^{-\frac{t}{\tau}} - \frac{16}{3\pi}e^{-\frac{t}{(1+3\lambda)\tau}}.
%\]
%
%The 50\% delay of wire 2 is approximated by
%\[
%T^{4C}_3\doteq\left(\ln{\frac{32}{3\pi}}\right)(1+3\lambda)\tau.
%\]
%
%
%\end{enumerate}


\subsection{Internal wires for five-wire model}\label{sec:5w}
To further improve the accuracy of delay, we include two extra adjacent wires to approximate the delay by considering the influences of all five wires. Each wire has three kinds of transition: $\uparrow$, -, and $\downarrow$. Hence, for such a five-wire bus, there are $3^5$ transition patterns. To maintain the simplicity of our models, we still divide them into five classes ($iC, \; i\in \{0,1,2,3,4\}$) based on the transition patterns of middle three wires (wires 2, 3, and 4). Hence, there are nine different transition patterns for each pattern of the same class.

Since the interconnect is a linear system, any pattern can be decomposed into a combination of patterns with transitions on a single wire. For example, $\u\u\u\d$- is decomposed as ($\u$- - - -) +  (-$\u$- - -) + (- -$\u$- -) + (- - -$\d$-). The delay expression of the middle wire impacted by any pattern is given by a summation of effects of individual wires on the middle wire.
%With the linear property, any pattern could be decomposed into a combination of expressions of each wire on the middle wire.
However, this approach would result in expressions that are hard to analyze. Instead, we propose to group these individual wires to form some special patterns, which can be analyzed easily.\\

\textbf{Definition 1}: Reducible transition pattern (RTP)

An RTP in the five-wire model is defined as a transition pattern that can be reduced to a transition pattern in the three-wire model. The set \{$\uparrow \uparrow \uparrow \uparrow \uparrow$, $\downarrow\downarrow\downarrow\downarrow\downarrow$, $\downarrow$-$\uparrow$-$\downarrow$, $\uparrow$-$\downarrow$-$\uparrow$\} is the set of RTPs for the five-wire model.

For the transition $\uparrow \uparrow \uparrow \uparrow \uparrow$ (similarly for $\downarrow \downarrow \downarrow \downarrow \downarrow$), all wires have the same transitions. There are no coupling capacitance between any two adjacent wires. So the expression of wire 3 is approximated by
%$V_3(t) = 1-e^{-\frac{t}{\tau_0}}$
$V_3(L,t) \doteq 1-\frac{4}{\pi}e^{-\frac{t}{\tau}}$ and the delay is approximated by $\left(\ln{\frac{8}{\pi}}\right)\tau$. For the transition $\downarrow$-$\uparrow$-$\downarrow$ (similarly for $\uparrow$-$\downarrow$-$\uparrow$), wires 2 and 4 can be approximated as ground wires in the five-wire bus, since wire 1 (or 5) and wire 3 have opposite transitions. For wire 3, the five-wire pattern is equivalent to a three-wire pattern $\downarrow \uparrow \downarrow$, where the equivalent coupling capacitor between wire 1 (or 5) and wire 3 is equal to two capacitors in series between wires 1 and 2, and wires 2 and 3 (or wires 3 and 4, and wires 4 and 5).
Hence, the equivalent coupling factor between wire 1 (or 5) and wire 3 is approximated as $\frac{\lambda}{2}$ per unit length (that is, the ratio of the coupling capacitance and the loading capacitance is $\frac{\lambda}{2}$). The expression of wire 3 is approximated by $V_3(L,t) \doteq 1+\frac{4}{3\pi} e^{-\frac{t}{\tau}} - \frac{16}{3\pi} e^{-\frac{t}{(1+\frac{3}{2}\lambda)\tau}}$, and the delay is approximated by $\ln (\frac{16}{3\pi})(1+\frac{3}{2}\lambda)\tau$.\\

\textbf{Definition 2}: Single transition pattern (STP)

%The STP is defined as \{-$\uparrow$-~-~-, -$\downarrow$-~-~-, -~-~-$\uparrow$-, -~-~-$\downarrow$-\}, which has single transition on wire 2 or 4.
An STP is defined to be a transition pattern with transitions on only one wire. For our five-wire model, we focus on the set of STPs with transitions on wire 2 or 4, \{-$\uparrow$-~-~-, -$\downarrow$-~-~-, -~-~-$\uparrow$-, -~-~-$\downarrow$-\}.

The expressions of wire 3 can be approximated by considering wires 2, 3, and 4 as a three-wire model. Let $V^{i}_j(x,t)$ denote the signal on wire $j$ due to coupling from wire $i$. For example, by ignoring coupling from wires 1 and 5 in -$\uparrow$- - -, the output of wire 3 is approximated by  $V^{2}_{3}(L,t)\doteq \textnormal{-}\frac{4}{3\pi}e^{-\frac{t}{\tau}}+\frac{4}{3\pi}e^{-\frac{t}{(1+3\lambda)\tau}}$, which is obtained by considering only wires 2, 3, and 4.\\

We propose the following approaches to derive the delay of the five-wire bus.
\begin{itemize}
\item We first \textbf{decompose} the worst pattern in each class into a combination of an RTP and STP(s).
\item Then we combine the expressions of the RTP and STP(s) for the middle wire based on the conclusion of our three-wire model.
\item Finally, we evaluate the expression of the middle wire to approximate its delay.
\end{itemize}

Since the performance is limited by the worst-case delay in each class, we need to approximate the delays of only the worst patterns in each class.
We use simulation to identify the worst patterns in all classes.
The worst patterns for $0C$ to $4C$ are given by $\downarrow \uparrow \uparrow \uparrow \downarrow$, $\downarrow \uparrow \uparrow$-$\downarrow$, $\downarrow$-$\uparrow$-$\downarrow$, $\uparrow \downarrow \uparrow$-$\uparrow$, and $\uparrow \downarrow \uparrow \downarrow \uparrow$, respectively (assuming the middle wire has an upward transition). With RTPs and STPs, we decompose the worst pattern in each class as shown in Table~\ref{tab:decomp}.
\begin{table}
\caption{Decomposition of worst-case patterns in the five-wire model.} \label{tab:decomp}
\begin{center}
\begin{tabular}{|c|c|l|}
\hline
$iC$ & Worst pattern & Decomposition\\
\hline
$0C$ & $\downarrow \uparrow \uparrow \uparrow \downarrow$ & ($\downarrow$-$\uparrow$-$\downarrow$)+(-$\uparrow$- - -)+( - - -$\uparrow$-)\\
\hline
$1C$ & $\downarrow$-$\uparrow \uparrow \downarrow$ & ($\downarrow$-$\uparrow$-$\downarrow$)+(- - -$\uparrow$-)\\
\hline
$2C$ & $\downarrow$-$\uparrow$-$\downarrow$ & ($\downarrow$-$\uparrow$-$\downarrow$)\\
\hline
$3C$ & $\uparrow$-$\uparrow \downarrow \uparrow$ & ($\uparrow \uparrow \uparrow \uparrow \uparrow$)+(- - -$\downarrow$-)+ (- - -$\downarrow$-) + (-$\downarrow$- - -)\\
\hline
$4C$ & $\uparrow \downarrow \uparrow \downarrow \uparrow$ & ($\uparrow \uparrow \uparrow \uparrow \uparrow$)+(-$\downarrow$- - -)+(-$\downarrow$- - -)+(- - -$\downarrow$-)+(- - -$\downarrow$-)\\
\hline
\end{tabular}
\end{center}
\end{table}


The closed-form expressions of wire 3 and approximate delays for all classes in a five-wire bus are derived and summarized in Table~\ref{tab:5wire}, where $T^{iC}_5$ the approximate delay for $iC$ pattern by our three-wire model.

\begin{table}[!t]
\caption{Closed-form expressions of signal on wire 3 and approximate delays in a five-wire bus ($V_3(L,t) = 1-A_3 e^{-\frac{t}{\tau}} - A_4 e^{-\frac{t}{(1+\frac{3}{2}\lambda)\tau}} - A_5 e^{-\frac{t}{(1+3\lambda)\tau}}$, $\tau_0=\frac{rcL^2}{2}$, and $\tau=\frac{8}{\pi^2}\tau_0$.)}\label{tab:5wire}
\begin{center}
\begin{tabular}{|c|c|c|c|c|c|}
\hline
\multirow{2}{*}{$iC$} & Worst & \multicolumn{3}{|c|}{Coeffs. of $V_3(L,t)$} & \multirow{2}{*}{$T_5^{iC}$}\\
\cline{3-5}
& Pattern & $A_3$ & $A_4$ & $A_5$ & \\
\hline
$0C$ & $\d\u\u\u\d$ & $\frac{4}{3\pi}$ & $\frac{16}{3\pi}$ & $\textnormal{-}\frac{8}{3\pi}$ & $0.165(1+3\lambda)\tau$ \\
\hline
$1C$ & $\d\u\u$-$\d$ & 0 & $\frac{16}{3\pi}$ & $\textnormal{-}\frac{4}{3\pi}$ & $0.384(1+3\lambda)\tau$\\
\hline
$2C$ & $\d$-$\u$-$\d$ & $\textnormal{-}\frac{4}{3\pi}$ & $\frac{16}{3\pi}$ & 0 & $\left(\ln{\frac{32}{3\pi}}\right)(1+\frac{3}{2}\lambda)\tau$ \\
\hline
$3C$ & $\u\d\u$-$\u$ & 0 & 0 & $\frac{4}{\pi}$ & $\left(\ln{\frac{8}{\pi}}\right)(1+3\lambda)\tau$ \\
\hline
%$4C$ & $\d\u\d$ & $-4/(3\pi)$ & $16/(3\pi)$ & $\left(\ln{\frac{32}{3\pi}}\right)(1+3\lambda)\tau$ \\
$4C$ & $\u\d\u\d\u$ & $\textnormal{-}\frac{4}{3\pi}$ & 0 & $\frac{16}{3\pi}$ & $\left(\ln{\frac{32}{3\pi}}\right)(1+3\lambda)\tau$ \\
\hline
\end{tabular}
\end{center}
\end{table}

%\begin{enumerate}
%\item $0C$ class:
%
%The worst-case pattern in $0C$ is $\downarrow \uparrow \uparrow \uparrow \downarrow$, which is a combination of $\downarrow$-$\uparrow$-$\downarrow$, -$\uparrow$- - -, and - - -$\uparrow$-. The output of wire 3 is approximated by
%\[
%V_3(L,t) \doteq 1-\frac{16}{3\pi}e^{-\frac{t}{(1+\frac{3}{2}\lambda)\tau}}+\frac{8}{3\pi}e^{-\frac{t}{(1+3\lambda)\tau}}.
%\]
%
%When $V_3(L,t)=0.5$, we have $e^{-\frac{t}{(1+3\lambda)\tau}} \doteq 0.848$. The 50\% delay of wire 3 is approximated by
%\[T^{0C}_5 \doteq 0.165(1+3\lambda)\tau.\]
%
%\item $1C$ class:
%
%The worst-case pattern in $1C$ is $\downarrow$-$\uparrow \uparrow \downarrow$, which is a combination of $\downarrow$-$\uparrow$-$\downarrow$ and - - -$\uparrow$-. The output of wire 3 is approximated by
%\[
%V_3(L,t) \doteq  1-\frac{16}{3\pi}e^{-\frac{t}{(1+\frac{3}{2}\lambda)\tau}}+\frac{4}{3\pi}e^{-\frac{t}{(1+3\lambda)\tau}}.
%\]
%
%When $V_3(L,t)=0.5$, we have $e^{-\frac{t}{(1+3\lambda)\tau}} \doteq 0.682$. The 50\% delay of wire 3 is approximated by
%\[T^{0C}_5 \doteq 0.310(1+3\lambda)\tau.\]
%
%
%\item $2C$ class:
%
%The worst-case pattern in $2C$ is $\downarrow$-$\uparrow$-$\downarrow$, which is just one of the RTPs. The output of wire 3 is approximated by
%\[
%V_3(L,t) \doteq  1+\frac{4}{3\pi}e^{-\frac{t}{\tau}}-\frac{16}{3\pi}e^{-\frac{t}{(1+\frac{3}{2}\lambda)\tau}}.
%\]
%
%The 50\% delay of wire 3 is approximated by
%\[
%T^{2C}_5\doteq\left(\ln{\frac{32}{3\pi}}\right)\left(1+\frac{3\lambda}{2}\right)\tau.
%\]
%
%\item $3C$ class:
%
%The worst-case pattern in $3C$ is $\uparrow$-$\uparrow \downarrow \uparrow$, which is a combination of $\uparrow\uparrow\uparrow\uparrow\uparrow$, -$\downarrow$- - -, - - -$\downarrow$-, and - - -$\downarrow$-. The output of wire 3 is approximated by
%\[
%V_3(L,t) \doteq  1-\frac{4}{\pi}e^{-\frac{t}{(1+3\lambda)\tau}}.
%\]
%
%The 50\% delay of wire 3 is approximated by
%\[
%T^{3C}_5\doteq\left(\ln{\frac{8}{\pi}}\right)(1+3\lambda)\tau.
%\]
%
%
%\item $4C$ class:
%
%The worst-case pattern in $4C$ is $\uparrow \downarrow \uparrow \downarrow \uparrow$, which is a combination of $\uparrow\uparrow\uparrow\uparrow\uparrow$, -$\downarrow$-~-~-, -$\downarrow$-~-~-, -~-~-$\downarrow$-, and -~-~-$\downarrow$-. The output of wire 3 is approximated by
%\[
%V_3(L,t) \doteq  1+\frac{4}{3\pi}e^{-\frac{t}{\tau}}-\frac{16}{3\pi}e^{-\frac{t}{(1+3\lambda)\tau}}.
%\]
%
%The 50\% delay of wire 3 is approximated by
%\[
%T^{4C}_5\doteq\left(\ln{\frac{32}{3\pi}}\right)(1+3\lambda)\tau.
%\]
%
%\end{enumerate}

\subsection{Boundary wires}
\label{sec:boundary}
In the previous derivation, we focus on middle wires and consider four neighboring wires (two to the left and two to the right) for crosstalk. In this section, we derive delay models to account for the boundary wires of an $m$-wire bus (wires 1, 2, $m-1$, and $m$). For wire 1 (wire $m$), we consider wires 2 and 3 to the right (wires $m-2$ and $m-1$ to the left) for crosstalk, and use the same classification as in Eq.~(\ref{Eq:1})~\cite{Sot01}. Note that for wires 1 and $m$, there are only three classes of patterns, $0C$, $1C$, and $2C$.
With the similar technique, the closed-form expressions of wire 1 (wire $m$) and approximate delays for all classes are derived and summarized in Table~\ref{tab:wire1}, where $T_{b1}^{iC}$ is the approximate delay for $iC$ pattern.
For wire 2 (wire $m-1$), we consider wire 1 to the left and wires 3 and 4 to the right (wires $m-3$, $m-2$ to the left and wire $m$ to the right) for crosstalk. Similarly, the closed-form expressions of wire 2 (wire $m-1$) and approximate delays for all classes are derived and summarized in Table~\ref{tab:wire2}, where $T_{b2}^{iC}$ is the approximate delay for $iC$ pattern.

\begin{table}[!t]
\caption{Closed-form expressions of signal on wire 1 and approximate delays ($V_1(L,t) = 1-A_6 e^{-\frac{t}{\tau}} - A_7 e^{-\frac{t}{(1+\lambda)\tau}} - A_8 e^{-\frac{t}{(1+3\lambda)\tau}}$, $\tau_0=\frac{rcL^2}{2}$, and $\tau=\frac{8}{\pi^2}\tau_0$.)}\label{tab:wire1}
\begin{center}
\begin{tabular}{|c|c|c|c|c|c|}
\hline
\multirow{2}{*}{$iC$} & Worst & \multicolumn{3}{|c|}{Coeffs. of $V_1(L,t)$} & \multirow{2}{*}{$T_{b1}^{iC}$}\\
\cline{3-5}
& Pattern & $A_6$ & $A_7$ & $A_8$ & \\
\hline
$0C$ & $\u\u\d$ & $\frac{4}{3\pi}$ & $\frac{4}{\pi}$ & $\textnormal{-}\frac{4}{3\pi}$ & $0.783(1+\lambda)\tau$ \\
\hline
$1C$ & $\u$-$\d$ & 0 & $\frac{4}{\pi}$ & 0 & $(\ln \frac{8}{\pi})(1+\lambda)\tau$\\
\hline
$2C$ & $\u\d\d$ & $\textnormal{-}\frac{4}{3\pi}$ & $\frac{4}{\pi}$ & $\frac{4}{3\pi}$ & $1.094(1+\lambda)\tau$ \\
\hline
\end{tabular}
\end{center}
\end{table}

\begin{table}[!t]
\caption{Closed-form expressions of signal on wire 2 and approximate delays ($V_2(L,t) = 1-A_9 e^{-\frac{t}{\tau}} - A_{10}e^{-\frac{t}{(1+2\lambda)\tau}} - A_{11} e^{-\frac{t}{(1+(2-\sqrt{2})\lambda)\tau}} - A_{12} e^{-\frac{t}{(1+(2+\sqrt{2})\lambda)\tau}}$, $\tau_0=\frac{rcL^2}{2}$, and $\tau=\frac{8}{\pi^2}\tau_0$.)}\label{tab:wire2}
\begin{center}
\begin{tabular}{|c|c|p{3mm}|p{3mm}|c|c|c|}
\hline
\multirow{2}{*}{$iC$} & Worst & \multicolumn{4}{|c|}{Coeffs. of $V_2(L,t)$} & \multirow{2}{*}{$T_{b2}^{iC}$}\\
\cline{3-6}
& Pattern & $A_9$ & $A_{10}$ & $A_{11}$ & $A_{12}$ & \\
\hline
$0C$ & $\u\u\u\d$ & $\frac{2}{\pi}$ & $\frac{2}{\pi}$ & $\frac{\sqrt{2}}{\pi}$ & $\textnormal{-}\frac{\sqrt{2}}{\pi}$ & $(\ln \frac{8}{\pi})\tau$ \\
\hline
$1C$ & -$\u\u\d$ & $\frac{1}{\pi}$ & $\frac{3}{\pi}$ & $\frac{\sqrt{2}}{2\pi}$ & $\textnormal{-}\frac{\sqrt{2}}{2\pi}$ & $0.427(1+2\lambda)\tau$\\
\hline
$2C$ & $\d\u\u\d$ & 0 & $\frac{4}{\pi}$ & 0 & 0 & $(\ln \frac{8}{\pi})(1+2\lambda)\tau$ \\
\hline
$3C$ & $\d\u$-$\u$ & $\frac{1}{\pi}$ & $\frac{1}{\pi}$ & $\frac{2-3\sqrt{2}}{2\pi}$ & $\frac{2+3\sqrt{2}}{2\pi}$ & $1.441(1+2\lambda)\tau$\\
\hline
\multirow{2}{*}{$4C$} & \multirow{2}{*}{$\d\u\d\u$} & \multirow{2}{*}{0} & \multirow{2}{*}{0} & \multirow{2}{*}{$\frac{2(1-\sqrt{2})}{\pi}$} & \multirow{2}{*}{$\frac{2(1+\sqrt{2})}{\pi}$} & $6.540(1+$ \\
& & & & & & $(2-\sqrt{2})\lambda)\tau$\\
\hline
\end{tabular}
\end{center}
\end{table}

\subsection{Revised models with consideration of the buffer effects}
\label{sec:revised}
In the previous derivation, the buffer effects are ignored with assumption that the driver resistance and loading capacitance are relatively small. In practice, the values of resistance and capacitance vary with different structure of buffers.
In this work, we consider drivers and receivers implemented as a non-inverting inverter chain. The simplest one has two chained inverters. The loading capacitance $C_L$ and driver resistance $R_S$ are due to the first and last stage inverters in the chain, respectively.
The buffer strength is measured by the normalized size of inverter to the smallest inverter.
%Hence, large buffer leads to small $R_S$ and large $C_L$.
For global interconnects in submicron technology, the loading capacitance is not significantly large in comparison with that of interconnect. According to~\cite{ANRS_TCASI08}, for a 45nm technology~\cite{FreePDK45}, the loading capacitance $C_L$ induced by a 100 times inverter is given by 25 fF. In this paper, we consider loading capacitance as large as 100 fF. For significantly large $C_L$, the delay due to $C_L$ would dominate the total propagation delay and all classes of patterns would collapse into one class.
In the following, we revise our models to capture the buffer effects of $R_S$ and $C_L$ at the inputs and outputs of the interconnects, respectively.

%However, the relative delays among all transition patterns would not change.
%However, the choice of buffers may impact the results significantly, if the driver resistance and loading capacitance are relatively large.
%The total delays would increase due to the buffer effects.



First, we focus on our three-wire model. With consideration of buffer effects, the differential equation is still given by Eq.~(\ref{Eq:2}). Only the boundary conditions need to be changed. The revised boundary conditions are given by
\begin{equation*}
\left\{\begin{array}{l}
V_i(0,t) = V_i^p-(V_i^p-V_i^f) u(t)-I_i(0,t) R_S \\
I_i(L,t)=C_L \frac{\partial}{\partial t}V_i(L,t) \quad\quad \mbox{ for } i=1,2,3
\end{array}  \right.
\end{equation*}


By solving the differential equations of a three-wire bus, we derive the expressions of all worst-case patterns as shown in Table~\ref{tab:3dif}.
The revised delay expressions are listed in column five of Table~\ref{tab:3dif}.
%The delay expressions are derived for the two cases: $C_T \ll 1$ and $C_T \gg 1$, as shown in Table~\ref{tab:3dif}, since the ratio of two time constants $\tau_1/\tau_2$ would change greatly with $C_L$.
Note that the revised three-wire delay model would reduce to that in Table~\ref{tab:3wire}, when the driver resistance and loading capacitance are relatively small, $R_T \doteq 0$ and $C_T \doteq 0$.
%For $C_T \gg 1$, the delay due to the loading capacitance would dominate the total delay and the approximate delays for all classes are the same.

%, where
%$K^3_1 = -1.01 \frac{R_T+C_T+1}{R_T+C_T+\frac{\pi}{4}}$, $K^3_2 = -1.01 \frac{R_T+C_T^\ast+1}{R_T+C_T^\ast+\frac{\pi}{4}}$, $\tau_1 = \frac{RC(R_TC_T+R_T+C_T+(\frac{2}{\pi})^2)}{1.04}$,  $\tau_2 = \frac{(1+3\lambda) RC(R_TC_T^\ast+R_T+C_T^\ast+(\frac{2}{\pi})^2)}{1.04}$,  $R_T=\frac{R_S}{rL}$, $C_T=\frac{C_L}{cL}$, $C_T^\ast=\frac{C_L}{(1+3\lambda)cL}$, $C=cL$, and $R=rL$.

%$K^3_1 = -1.01 (R_T+C_T+1)/(R_T+C_T+\pi/4)$, $K^3_2 = -1.01 (R_T+C_T^\ast+1)/(R_T+C_T^\ast+\pi/4)$, $\tau_1 = RC(R_TC_T+R_T+C_T+(\frac{2}{\pi})^2)/1.04$,  $\tau_2 = (1+3\lambda) RC(R_TC_T^\ast+R_T+C_T^\ast+(\frac{2}{\pi})^2)/1.04$,  $R_T=R_S/(rL)$, $C_T=C_L/(cL)$, $C_T^\ast=C_L/((1+3\lambda)cL)$, $C=cL$, and $R=rL$.


%\begin{table}[!thb]
%\caption{Expressions of middle wire in a three-wire model, where $V_2(L,t) = 1 - b_1 B_1 e^{-\frac{t}{\tau_1}} - b_2 B_2 e^{-\frac{t}{\tau_2}}$, $B_1 = 1.01\frac{R_T+C_T+1}{R_T+C_T+\frac{\pi}{4}}$, $B_2 = 1.01\frac{R_T+C_T^\ast+1}{R_T+C_T^\ast+\frac{\pi}{4}}$, $\tau_1 = \frac{RC(R_TC_T+R_T+C_T+(\frac{2}{\pi})^2)}{1.04}$,  $\tau_2 = \frac{(1+3\lambda) RC(R_TC_T^\ast+R_T+C_T^\ast+(\frac{2}{\pi})^2)}{1.04}$,  $R_T=\frac{R_S}{R}$, $C_T=\frac{C_L}{C}$, $C_T^\ast=\frac{C_L}{(1+3\lambda)C}$, $C=cL$, and $R=rL$.} \label{tab:3dif}
%\begin{center}
%\begin{tabular}{|c|c|c|c|c|c|}
%\hline
%\multirow{2}{*}{$iC$} & Worst & \multicolumn{2}{|c|}{Coeffs. of $V_2(L,t)$} & \multicolumn{2}{|c|}{$T_3^{iC}$}\\
%\cline{3-6}
%& Pattern & $b_1$ & $b_2$ & $C_T \ll 1$ & $C_T \gg 1$ \\
%\hline
%$0C$ & $\u\u\u$ & 1 & 0 & $(\ln 2B_1)\tau_1$ & $(\ln 2)\tau_2$ \\
%\hline
%$1C$ & $\u\u$- & $\frac{2}{3}$ & $\frac{1}{3}$ & $(\ln 4B_1)\tau_1$ & $(\ln 2)\tau_2$ \\
%\hline
%$2C$ & -$\u$- & $\frac{1}{3}$ & $\frac{2}{3}$ & $(\ln \frac{4B_2}{3})\tau_2$ & $(\ln 2)\tau_2$ \\
%\hline
%$3C$ & $\d\u$- & 0 & 1 & $(\ln 2B_2)\tau_2$ & $(\ln 2)\tau_2$ \\
%\hline
%$4C$ & $\d\u\d$ & $\textnormal{-}\frac{1}{3}$ & $\frac{4}{3}$ & $(\ln \frac{8B_2}{3})\tau_2$ & $(\ln 2)\tau_2$ \\
%\hline
%\end{tabular}
%\end{center}
%\end{table}

\begin{table}[!t]
\caption{Expressions of middle wire in a three-wire model, where $V_2(L,t) = 1 - b_1 B_1 e^{-\frac{t}{\tau_1}} - b_2 B_2 e^{-\frac{t}{\tau_2}}$, $B_1 = 1.01\frac{R_T+C_T+1}{R_T+C_T+\frac{\pi}{4}}$, $B_2 = 1.01\frac{R_T+C_T^\ast+1}{R_T+C_T^\ast+\frac{\pi}{4}}$, $\tau_1 = \frac{RC(R_TC_T+R_T+C_T+(\frac{2}{\pi})^2)}{1.04}$,  $\tau_2 = \frac{(1+3\lambda) RC(R_TC_T^\ast+R_T+C_T^\ast+(\frac{2}{\pi})^2)}{1.04}$,  $R_T=\frac{R_S}{R}$, $C_T=\frac{C_L}{C}$, $C_T^\ast=\frac{C_L}{(1+3\lambda)C}$, $C=cL$, and $R=rL$.} \label{tab:3dif}
\begin{center}
\begin{tabular}{|c|c|c|c|c|}
\hline
\multirow{2}{*}{$iC$} & Worst & \multicolumn{2}{|c|}{Coeffs. of $V_2(L,t)$} & \multirow{2}{*}{$T_3^{iC}$}\\
\cline{3-4}
& Pattern & $b_1$ & $b_2$ & \\
\hline
$0C$ & $\u\u\u$ & 1 & 0 & $(\ln 2B_1)\tau_1$ \\
\hline
$1C$ & $\u\u$- & $\frac{2}{3}$ & $\frac{1}{3}$ & $(\ln 4B_1)\tau_1$ \\
\hline
$2C$ & -$\u$- & $\frac{1}{3}$ & $\frac{2}{3}$ & $(\ln \frac{4B_2}{3})\tau_2$ \\
\hline
$3C$ & $\d\u$- & 0 & 1 & $(\ln 2B_2)\tau_2$ \\
\hline
$4C$ & $\d\u\d$ & $\textnormal{-}\frac{1}{3}$ & $\frac{4}{3}$ & $(\ln \frac{8B_2}{3})\tau_2$ \\
\hline
\end{tabular}
\end{center}
\end{table}


\begin{table}[!t]
\caption{Expressions of middle wire in a five-wire model, where $V_3(L,t) = 1 - b_3 B_3 e^{-\frac{t}{\tau_1}} - b_4 B_4 e^{-\frac{t}{\tau_2}} - b_5 B_5 e^{-\frac{t}{\tau_3}}$, $B_3 = 1.01\frac{R_T+C_T+1}{R_T+C_T+\frac{\pi}{4}}$, $B_4 = 1.01\frac{R_T+C_T^\ast+1}{R_T+C_T^\ast+\frac{\pi}{4}}$, $B_5 = 1.01\frac{R_T+C_T^\dagger+1}{R_T+C_T^\dagger+\frac{\pi}{4}}$, $\tau_1 = \frac{RC(R_TC_T+R_T+C_T+(\frac{2}{\pi})^2)}{1.04}$,  $\tau_2 = \frac{(1+\frac{3}{2}\lambda) RC(R_TC_T^\ast+R_T+C_T^\ast+(\frac{2}{\pi})^2)}{1.04}$, $\tau_3 = \frac{(1+3\lambda) RC(R_TC_T^\dagger+R_T+C_T^\dagger+(\frac{2}{\pi})^2)}{1.04}$,  $R_T=\frac{R_S}{R}$, $C_T=\frac{C_L}{C}$, $C_T^\ast=\frac{C_L}{(1+\frac{3\lambda}{2})C}$, $C_T^\dagger=\frac{C_L}{(1+3\lambda)C}$, $C=cL$, $R=rL$, $f_1 = (\textnormal{-}\ln (\frac{1}{4}+\frac{1}{2} \sqrt{\frac{1}{4}+\frac{3}{2 B_5}}))$, and $f_2 = (\textnormal{-}\ln (\frac{1}{8}+\frac{1}{2}\sqrt{\frac{1}{16}+\frac{3}{2 B_5}}))$.} \label{tab:5dif}
\begin{center}
\begin{tabular}{|c|c|c|c|c|c|}
\hline
\multirow{2}{*}{$iC$} & Worst & \multicolumn{3}{|c|}{Coeffs. of $V_3(L,t)$} & \multirow{2}{*}{$T_5^{iC}$}\\
\cline{3-5}
& Pattern & $b_3$ & $b_4$ & $b_5$ & \\
\hline
$0C$ & $\d\u\u\u\d$ & $\frac{1}{3}$ & $\frac{4}{3}$ & $\textnormal{-}\frac{2}{3}$ & $f_1\tau_3$ \\
\hline
$1C$ & $\d\u\u$-$\d$ & 0 & $\frac{4}{3}$ & $\textnormal{-}\frac{1}{3}$ & $f_2\tau_3$ \\
\hline
$2C$ & $\d$-$\u$-$\d$ & $\textnormal{-}\frac{1}{3}$ & $\frac{4}{3}$ & 0 & $(\ln \frac{8 B_4}{3})\tau_2$ \\
\hline
$3C$ & $\u\d\u$-$\u$ & 0 & 0 & 1 & $(\ln 2 B_5)\tau_3$ \\
\hline
%$4C$ & $\d\u\d$ & $-4/(3\pi)$ & $16/(3\pi)$ & $\left(\ln{\frac{32}{3\pi}}\right)(1+3\lambda)\tau$ \\
$4C$ & $\u\d\u\d\u$ & $\textnormal{-}\frac{1}{3}$ & 0 & $\frac{4}{3}$ & $(\ln \frac{8 B_5}{3})\tau_3$ \\
\hline
\end{tabular}
\end{center}
\end{table}


%\begin{table}
%\caption{Expressions of middle wire in a three-wire model, where $K^3_1 = -1.01 \frac{R_T+C_T+1}{R_T+C_T+\frac{\pi}{4}}$, $K^3_2 = -1.01 \frac{R_T+C_T^\ast+1}{R_T+C_T^\ast+\frac{\pi}{4}}$, $\tau_1 = \frac{RC(R_TC_T+R_T+C_T+(\frac{2}{\pi})^2)}{1.04}$,  $\tau_2 = \frac{(1+3\lambda) RC(R_TC_T^\ast+R_T+C_T^\ast+(\frac{2}{\pi})^2)}{1.04}$,  $R_T=\frac{R_S}{rL}$, $C_T=\frac{C_L}{cL}$, $C_T^\ast=\frac{C_L}{(1+3\lambda)cL}$, $C=cL$, and $R=rL$.} \label{tab:3dif}
%\begin{center}
%\begin{tabular}{|c|c|c|}
%\hline
%$iC$ & $V_2(L,t)$ & Delay\\
%\hline
%$0C$ & $1-K^3_1 e^{-\frac{t}{\tau_1}}$ & $(\ln 2K^3_1)\tau_1$\\
%\hline
%$1C$ & $1-\frac{2}{3}K^3_1 e^{-\frac{t}{\tau_1}}-\frac{1}{3}K^3_2 e^{-\frac{t}{\tau_2}}$ & $(\ln 4K^3_1)\tau_1$\\
%\hline
%$2C$ & $1-\frac{1}{3}K^3_1 e^{-\frac{t}{\tau_1}}-\frac{2}{3}K^3_2 e^{-\frac{t}{\tau_2}}$ & $(\ln \frac{4K^3_2}{3})\tau_2$\\
%\hline
%$3C$ & $1-K^3_2 e^{-\frac{t}{\tau_2}}$ & $(\ln 2K^3_2)\tau_2$\\
%\hline
%$4C$ & $1+\frac{1}{3}K^3_1 e^{-\frac{t}{\tau_1}}-\frac{4}{3}K^3_2 e^{-\frac{t}{\tau_2}}$ & $(\ln \frac{8K^3_2}{3})\tau_2$\\
%\hline
%\end{tabular}
%\end{center}
%\end{table}

Similarly, for a five-wire bus, we derive the expressions of all worst-case patterns in each class as shown in Table~\ref{tab:5dif}.
%Like the revised three-wire model, we derive the delay expressions for the two cases: $C_T \ll 1$ and $C_T \gg 1$.
%All the delays can be approximated as closed-form expressions except for $0C$ and $1C$ classes, since the worst-case expressions of $0C$ and $1C$ classes contain two dominating exponents, which make it hard to approximate the delays in closed form.
The ratio between $\tau_2$ and $\tau_3$ is given by $\frac{\tau_2}{\tau_3}=\frac{(1+\frac{3}{2}\lambda) RC (R_TC_T^\ast+R_T+C_T^\ast+(\frac{2}{\pi})^2) }{(1+3\lambda) RC(R_TC_T^\dagger+R_T+C_T^\dagger+(\frac{2}{\pi})^2)} \doteq \frac{1}{2}$. Then the 50\% delay can be solved by assuming $e^{-\frac{t}{\tau_2}} = (e^{-\frac{t}{\tau_3}})^2$. The revised delay expressions are listed in column six of Table~\ref{tab:5dif}.
%For $C_T \gg 1$, the ratio is given by $\frac{\tau_2}{\tau_3} \doteq 1$. The revised five-wire model is shown in Table~\ref{tab:5dif}.
Note that the revised five-wire delay model would reduce to that in Table~\ref{tab:5wire}, when the driver resistance and loading capacitance are relatively small, $R_T \doteq 0$ and $C_T \doteq 0$.
%For $C_T \gg 1$, the delay due to the loading capacitance would dominate the total delay and the approximate delays for all classes are the same.

%%All the delays can be approximated as closed-form expressions, except for $0C$ and $1C$ classes, since the worst-case expressions of $0C$ and $1C$ classes contain two dominating exponents, which make it hard to approximate the delays in closed form.
%%All the expressions and revised five-wire delay model ($0C$ and $1C$ are discussed separately) are summarized in Table~\ref{tab:5dif}. Note that the revised five-wire delay model would reduce to that in Table~\ref{tab:5wire}, when the driver resistance and loading capacitance are relatively small, $R_T \doteq 0$ and $C_T \doteq 0$.
%
%
%
%To approximate the worst-case delays in $0C$ and $1C$ classes, we need to relate the two dominating exponents. The ratio between $\tau_2$ and $\tau_3$ is given by $\frac{\tau_2}{\tau_3}=\frac{(1+\frac{3}{2}\lambda) RC (R_TC_T^\ast+R_T+C_T^\ast+(\frac{2}{\pi})^2) }{(1+3\lambda) RC(R_TC_T^\dagger+R_T+C_T^\dagger+(\frac{2}{\pi})^2)}$.
%
%We discuss the ratio for $0C$ and $1C$ as follows.
%
%\begin{enumerate}
%\item If $R_T$, $C_T^\ast$, and $C_T^\dagger$ are insignificant:
%
%This is the case that the effect of drivers and receivers is insignificant and ignored for derivation. The ratio is given by $\frac{\tau_2}{\tau_3} \doteq \frac{1}{2}$. The worst-case delays of $0C$ and $1C$ are given by $0.165(1+3\lambda)(\frac{2}{\pi})^2 RC$ and $0.384(1+3\lambda)(\frac{2}{\pi})^2 RC$, respectively.
%
%
%\item If $R_T$ is significant, and $C_T^\ast$ and $C_T^\dagger$ are insignificant:
%
%The ratio is given by $\frac{\tau_2}{\tau_3} \doteq \frac{1}{2}$. $B_4 \doteq B_5$. The worst-case delays of $0C$ and $1C$ are given by
%$(\textnormal{-}\ln (\frac{1}{4}+\frac{1}{2}\sqrt{\frac{1}{4}+\frac{3}{2 B_4}})) \tau_3$ and $(\textnormal{-}\ln (\frac{1}{8}+\frac{1}{2}\sqrt{\frac{1}{16}+\frac{3}{2 B_4}})) \tau_3$, respectively.
%%$0.093(1+3\lambda)R_S C$ and $(\ln \frac{4}{3})(1+3\lambda)R_S C$, respectively.
%
%
%\item If $R_T$ is insignificant, and $C_T^\ast$ and $C_T^\dagger$ are significant:
%
%The ratio is given by $\frac{\tau_2}{\tau_3} \doteq \frac{1}{1}$. The worst-case delays of $0C$ and $1C$ are given by
%$(\textnormal{-}\ln \frac{3}{4(2 B_4 - B_5)})\tau_3$ and $(\textnormal{-}\ln \frac{3}{2(4 B_4 - B_5)})\tau_3$, respectively.
%%$(\ln \frac{4}{3})R C_L$ and $(\ln 2)R C_L$, respectively.
%
%
%\item If $R_T$, $C_T^\ast$, and $C_T^\dagger$ are significant:
%
%The ratio is given by $\frac{\tau_2}{\tau_3} \doteq \frac{1}{1}$. The worst-case delays of $0C$ and $1C$ are given by
%$(\textnormal{-}\ln \frac{3}{4(2 B_4 - B_5)})\tau_3$ and $(\textnormal{-}\ln \frac{3}{2(4 B_4 - B_5)})\tau_3$, respectively.
%\end{enumerate}

\begin{table}[!t]
\caption{Bus parameters in a 45$\mathrm{nm}$ technology.} \label{tab:parameter}
\begin{center}
\begin{tabular}{|c|c||c|c|}
\hline
\multicolumn{4}{|c|}{Parameters} \\
\hline
$L$ & 5 mm & $r$ & 13.75 $\Omega$/mm \\
\hline
$w$ & 0.8 $\mu$m & $l$ & 1.736 nH/mm \\
\hline
$s$ & 0.8 $\mu$m & $c$ & 8.263 fF/mm \\
\hline
$t$ & 2 $\mu$m & $c_c$ & 101.136 fF/mm \\
\hline
$h$ & 4.82 $\mu$m & $R_S$ & 100 $\Omega$ \\
\hline
$K_{\textrm{ILD}}$ & 2.5 & $C_L$ & 0 fF \\
\hline
\end{tabular}
\end{center}
\end{table}

According to the delay expressions in Tables~\ref{tab:3dif} and \ref{tab:5dif}, both driver resistance and loading capacitance tend to increase the delay. When the loading capacitance increases, the delay difference among all classes diminishes. For extremely large $C_L$, the delays for all classes are close and the classification becomes inconsequential.
%However, when $C_T \ll 1$, the driver resistance would not change the classification and the coding schemes for crosstalk delay reduction still work.

%\begin{table}[!thb]
%\caption{Expressions of middle wire in a five-wire model, where $V_3(L,t) = 1 - b_3 B_3 e^{-\frac{t}{\tau_1}} - b_4 B_4 e^{-\frac{t}{\tau_2}} - b_5 B_5 e^{-\frac{t}{\tau_3}}$, $B_3 = 1.01\frac{R_T+C_T+1}{R_T+C_T+\frac{\pi}{4}}$, $B_4 = 1.01\frac{R_T+C_T^\ast+1}{R_T+C_T^\ast+\frac{\pi}{4}}$, $B_5 = 1.01\frac{R_T+C_T^\dagger+1}{R_T+C_T^\dagger+\frac{\pi}{4}}$, $\tau_1 = \frac{RC(R_TC_T+R_T+C_T+(\frac{2}{\pi})^2)}{1.04}$,  $\tau_2 = \frac{(1+\frac{3}{2}\lambda) RC(R_TC_T^\ast+R_T+C_T^\ast+(\frac{2}{\pi})^2)}{1.04}$, $\tau_3 = \frac{(1+3\lambda) RC(R_TC_T^\dagger+R_T+C_T^\dagger+(\frac{2}{\pi})^2)}{1.04}$,  $R_T=\frac{R_S}{R}$, $C_T=\frac{C_L}{C}$, $C_T^\ast=\frac{C_L}{(1+\frac{3\lambda}{2})C}$, $C_T^\dagger=\frac{C_L}{(1+3\lambda)C}$, $C=cL$, $R=rL$, $f_1 = (\textnormal{-}\ln (\frac{1}{4}+\frac{1}{2} \sqrt{\frac{1}{4}+\frac{3}{2 B_5}}))$, and $f_2 = (\textnormal{-}\ln (\frac{1}{8}+\frac{1}{2}\sqrt{\frac{1}{16}+\frac{3}{2 B_5}}))$.} \label{tab:5dif}
%\begin{center}
%\begin{tabular}{|c|c|c|c|c|c|c|}
%\hline
%\multirow{2}{*}{$iC$} & Worst & \multicolumn{3}{|c|}{Coeffs. of $V_3(L,t)$} & \multicolumn{2}{|c|}{$T_5^{iC}$}\\
%\cline{3-7}
%& Pattern & $b_3$ & $b_4$ & $b_5$ & $C_T \ll 1$ & $C_T \gg 1$ \\
%\hline
%$0C$ & $\d\u\u\u\d$ & 0 & $\frac{4}{3}$ & $\textnormal{-}\frac{2}{3}$ & $f_1\tau_3$ & $(\ln 2) \tau_3$ \\
%\hline
%$1C$ & $\d\u\u$-$\d$ & 0 & $\frac{4}{3\pi}$ & $\textnormal{-}\frac{1}{3}$ & $f_2\tau_3$ & $(\ln 2) \tau_3$ \\
%\hline
%$2C$ & $\d$-$\u$-$\d$ & $\textnormal{-}\frac{1}{3}$ & $\frac{4}{3}$ & 0 & $(\ln \frac{8 B_4}{3})\tau_2$ & $(\ln 2) \tau_3$ \\
%\hline
%$3C$ & $\u\d\u$-$\u$ & 0 & 0 & 1 & $(\ln 2 B_5)\tau_3$ & $(\ln 2) \tau_3$ \\
%\hline
%%$4C$ & $\d\u\d$ & $-4/(3\pi)$ & $16/(3\pi)$ & $\left(\ln{\frac{32}{3\pi}}\right)(1+3\lambda)\tau$ \\
%$4C$ & $\u\d\u\d\u$ & $\textnormal{-}\frac{1}{3}$ & 0 & $\frac{4}{3}$ & $(\ln \frac{8 B_5}{3})\tau_3$ & $(\ln 2) \tau_3$ \\
%\hline
%\end{tabular}
%\end{center}
%\end{table}




%\begin{table}
%\caption{Expressions of middle wire in a five-wire model, where $K^5_1 = \textnormal{-}1.01 \frac{R_T+C_T+1}{R_T+C_T+\frac{\pi}{4}}$, $K^5_2 = \textnormal{-}1.01 \frac{R_T+C_T^\ast+1}{R_T+C_T^\ast+\frac{\pi}{4}}$, $K^5_3 = \textnormal{-}1.01 \frac{R_T+C_T^\dagger+1}{R_T+C_T^\dagger+\frac{\pi}{4}}$, $\tau_1 = \frac{RC(R_TC_T+R_T+C_T+(\frac{2}{\pi})^2)}{1.04}$,  $\tau_2 = \frac{(1+\frac{3}{2}\lambda) RC(R_TC_T^\ast+R_T+C_T^\ast+(\frac{2}{\pi})^2)}{1.04}$, $\tau_3 = \frac{(1+3\lambda) RC(R_TC_T^\dagger+R_T+C_T^\dagger+(\frac{2}{\pi})^2)}{1.04}$,  $R_T=\frac{R_S}{rL}$, $C_T=\frac{C_L}{cL}$, $C_T^\ast=\frac{C_L}{(1+\frac{3\lambda}{2})cL}$, $C_T^\dagger=\frac{C_L}{(1+3\lambda)cL}$, $C=cL$, and $R=rL$.} \label{tab:5dif}
%\begin{center}
%\begin{tabular}{|c|c|c|}
%\hline
%$iC$ & $V_3(L,t)$ & Delay\\
%\hline
%$0C$ & $1+\frac{4}{3}K^5_2 e^{-\frac{t}{\tau_2}}-\frac{2}{3}K^5_3 e^{-\frac{t}{\tau_3}}$ & --- \\
%\hline
%$1C$ & $1+\frac{4}{3}K^5_2 e^{-\frac{t}{\tau_2}}-\frac{1}{3}K^5_3 e^{-\frac{t}{\tau_3}}$ & --- \\
%\hline
%$2C$ & $1-\frac{1}{3}K^5_1 e^{-\frac{t}{\tau_1}}+\frac{4}{3}K^5_2 e^{-\frac{t}{\tau_2}}$ & $(\ln \frac{8K^5_2}{3})\tau_2$\\
%\hline
%$3C$ & $1-K^5_3 e^{-\frac{t}{\tau_3}}$ & $(\ln 2K^5_3)\tau_3$\\
%\hline
%$4C$ & $1-\frac{1}{3}K^5_1 e^{-\frac{t}{\tau_1}}+\frac{4}{3}K^5_3 e^{-\frac{t}{\tau_3}}$ & $(\ln \frac{8K^5_3}{3})\tau_3$\\
%\hline
%\end{tabular}
%\end{center}
%\end{table}

\subsection{Characterization of the delay of a multi-wire bus}
\label{sec:application}
%In the derivation of our models above, we focus only on the worst-case patterns of the middle wires. While the worst-case delay of a given transition pattern might happen on any wire of the whole bus.
%We assume that the worst-case delays of the middle wire and any other wire are close provided the two corresponding transitions focusing on the two wires belong to the same class. Though this is not obvious, we verify our assumption with extensive simulations in Sec.~\ref{sec:simulation}.

%To characterize the whole bus transition, our five-wire model is used to scan all the transition patterns of five adjacent wires.
%Our five-wire model can be easily applied to approximate the delays for all wires, except for boundary wires. For an $m$-wire bus ($m>5$), our  five-wire model can be applied to wire $i$ provided that $i\neq 1, 2, m-1, m$. That is, the delay of wire $i$ can be determined based on the transitions on wires $i-2, i-1, i, i+1, i+2$.
%For boundary wires in an $m$-wire bus, i.e., wires $1$, $2$, $m-1$, and $m$, we apply the same classification as in \cite{Sot01}. For wire $1$, we consider four cases. (1) If wire $1$ has no transition, the point is moot. (2) If wires $1$ and $2$ have the same transition, the pattern is classified as $0C$ for wire $1$. (3) If wire $1$ has a transition but wire $2$ has no transition, the pattern is classified as $1C$ for wire $1$. (4) If wires $1$ and $2$ have opposite transitions, the pattern is classified as $2C$. Similarly, for wire 2 ($m-1$), we consider transitions of adjacent wires $1$ and $3$, and identify the pattern class on wires $1$, $2$, and $3$. Due to symmetry, wires $m-1$ and $m$ can be dealt with in the same fashion.

In the derivation of our five-wire model above, we focus on the worst-case patterns of the middle wires only.
We also derive delay models for boundary wires. In the following, we show that our five-wire model can be easily applied to approximate the delays of an $m$-wire bus ($m>5$).
%To characterize the delay of the whole bus, the following scheme is used.
First, we use our five-wire delay model as a shift window to scan the internal wires (wires 3 through $m-2$) to identify the longest delay.
%Based on our five-wire model, we consider a shift windows of size 5, where four neighboring wires (two to the left and two to the right) are considered for crosstalk, since farther wires have weaker coupling effects.
%The shift window works for wires 3 through $m-3$.
Then, for boundary wires (wires 1, 2, $m-1$, and $m$), we use the models in Tables~\ref{tab:wire1} and \ref{tab:wire2} for delay approximation. Hence, the delay of an $m$-wire bus is given by the largest delay among all wires.
%To fill up the unmatched wires of interested boundary wire, we add some virtual wire(s) with the same transition as the outmost wire near the interested wire, since the additional virtual wires would not induce crosstalk. For instance, for the shift window with size 5, wires 1, 2, $m-1$, and $m$ are boundary wires. For wire 1 ($m$), we introduce wires $\textnormal{-}$1 and 0 ($m+1$ and $m+2$) as virtual wires with same transition as wire 1 ($m$), and consider the transition pattern on wires $\textnormal{-}$1, 0, 1, 2, and 3 ($m-2$, $m-1$, $m$, $m+1$, and $m+2$), which determines the delay on wire 1 ($m$). Similarly, for wire 2 ($m-1$), we introduce wire 0 ($m+1$) as virtual wire with same transition as wire 1 ($m$), and consider the transition pattern on wires 0, 1, 2, 3, and 4 ($m-3$, $m-2$, $m-1$, $m$, and $m+1$). Hence, our model can be applied to any wire in an $m$-wire bus, and the delay of the whole bus is given by the largest delay among all wires.
%For example, for a pattern $\u\d\u\d\d\d$ of a six-wire bus, the scanned patterns are $\U\U\u\d\u$, $\U\u\d\u\d$, $\u\d\u\d\d$, $\d\u\d\d\d$, $\u\d\d\d\D$, and $\d\d\d\D\D$ for wires 1 through 6, respectively, where $\U$ and $\D$ denote up and down transitions on virtual wires, respectively. The pattern classes are given by $2C$, $4C$, $4C$, $2C$, $0C$, and $0C$ for wires $1$ through $6$, respectively.
For example, for a pattern $\u\d\u\d\d\d$ of a six-wire bus, the classes for wires 1 through 6 are given by $2C$, $4C$, $4C$, $2C$, $0C$, and $0C$, respectively. Thus, the worst-case class is given by $4C$. According to our models in Tables~\ref{tab:5wire}, \ref{tab:wire1}, and \ref{tab:wire2}, the worst-case delay is given by the larger one of the two delays $6.540(1+(2-\sqrt{2})\lambda)\tau$ and $\left(\ln{\frac{32}{3\pi}}\right)(1+3\lambda)\tau$.

The proposed analytical delay models target two important applications. One primary application of our model is the design of crosstalk avoidance codes (CACs). Since our proposed models provide more accurate delays for different transition patterns than previous models, we can identify unwanted patterns more effectively. Second, our models can be applied to partial coding schemes, where buses are broken into sub-buses, since our models are more accurate for a bus of small size.
To incorporate such analytical delay models in EDA softwares, such as a typical timing analysis flow, appropriate adjustments are needed. We plan to investigate this important scenario in our future work.
%However, it may be difficult to incorporate such analytical delay models in EDA softwares in their simple forms. Our model is not suitable for applications requiring upper bounds on delays, such as a typical timing analysis flow.

%Our model is suitable for the general CAC design, where accurate classification is more important. Since our proposed model gives improved approximate delays for different transition patterns, we can identify unwanted patterns more precisely. This helps to decide which CAC is better to use. Since our model is more accurate for a bus of small size, our model can also be applied partial coding schemes. However, our model is not suitable for applications requiring conservative approximation, such as a typical timing analysis flow.


%\begin{table*}
%\caption{Comparison of simulated delays, delays of our three-wire model and the model in \cite{Sot01} ($\tau_0=3.75\mathrm{ps}$,~$\tau=\frac{8}{\pi^2}\tau_0$, and $\lambda=10$)}\label{tab:1}
%\begin{center}
%\begin{tabular}{|r|c|c|c|c|c|c|c|c|}
%\hline
%\multirow{2}{*}{$iC$}& \multirow{2}{*}{Worst pattern} & Sim. & \multicolumn{3}{|c|}{Our model} & \multicolumn{3}{|c|}{\cite{Sot01}}\\
%\cline{3-9} & & $T_d$ (ps) & $T^{iC}_3$ & (ps) & $\frac{|T^{iC}_3-T_d|}{T_d}$ & $T_2$ in (\ref{Eq:1}) & (ps) &  $\frac{|T_2-T_d|}{T_d}$\\
%\hline
%$0C$ & $\uparrow \uparrow \uparrow$ & 2.87 &  $\left(\ln{\frac{8}{\pi}}\right)\tau$ & 2.84 & 1.05\% & $\tau_0$ & 3.75  & 30.66\%\\
%\hline
%$1C$ & $\uparrow \uparrow$- & 4.99 & $\left(\ln{\frac{16}{\pi}}\right)\tau$  & 4.94 & 1.00\% & $(1+\lambda) \tau_0$ & 41.25  & 726.65\%\\
%\hline
%$2C$ & -$\uparrow$- & 49.70 & $\left(\ln{\frac{16}{3\pi}}\right)(1+3\lambda)\tau$  & 49.87 &  0.34\% & $ (1+2\lambda)\tau_0$ & 78.75 & 58.45\%\\
%\hline
%$3C$ & $\downarrow \uparrow$- & 88.61 & $\left(\ln{\frac{8}{\pi}}\right)(1+3\lambda)\tau$ & 88.08 &  0.60\% & $(1+3\lambda)\tau_0$ & 116.25 & 31.19\%\\
%\hline
%$4C$ & $\downarrow \uparrow \downarrow$ & 115.89 & $\left(\ln{\frac{32}{3\pi}}\right)(1+3\lambda)\tau$ & 115.18 & 0.61\% & $(1+4\lambda)\tau_0$ & 153.75  & 32.67\%\\
%\hline
%\end{tabular}
%\end{center}
%\end{table*}


%\begin{table*}
%\caption{Comparison of simulated delays, delays of our five-wire model and the model in \cite{Sot01} ($\tau_0=3.75\mathrm{ps}$,~$\tau=\frac{8}{\pi^2}\tau_0$, and $\lambda=10$).}\label{tab:2}
%\begin{center}
%\begin{tabular}{|r|c|c|c|c|c|c|c|c|}
%\hline
%\multirow{2}{*}{$iC$} & \multirow{2}{*}{Worst pattern} & Sim. & \multicolumn{3}{|c|}{Our model} & \multicolumn{3}{|c|}{\cite{Sot01}}\\
%\cline{3-9} & &  $T_d$ (ps) & $T^{iC}_5$ & (ps) & $\frac{|T^{iC}_5-T_d|}{T_d}$ & $T_3$ in (\ref{Eq:1}) & (ps) &  $\frac{|T_3-T_d|}{T_d}$\\
%\hline
%$0C$ & $\downarrow \uparrow \uparrow \uparrow \downarrow$ & 23.30 &  $0.165(1+3\lambda)\tau$ & 19.18 & 17.68\% & $\tau_0$ & 3.75  & 83.91\%\\
%\hline
%$1C$ & $\downarrow$-$\uparrow \uparrow \downarrow$ & 37.42 & $0.310(1+3\lambda) \tau$  & 34.99 & 6.49\% & $(1+\lambda) \tau_0$ & 41.25  & 10.24\%\\
%\hline
%$2C$ & $\downarrow$-$\uparrow$-$\downarrow$ & 56.58& $\left(\ln \frac{32}{3\pi}\right)\left(1+\frac{3}{2}\lambda\right)\tau$  & 59.46 &  5.09\% & $ (1+2\lambda)\tau_0$ & 78.75 & 39.18\%\\
%\hline
%$3C$ & $\uparrow$-$\uparrow \downarrow \uparrow$ & 88.55 & $\left(\ln{\frac{8}{\pi}}\right)(1+3\lambda)\tau$ & 88.08 &  0.53\% & $(1+3\lambda)\tau_0$ & 116.25 & 31.28\%\\
%\hline
%$4C$ & $\uparrow \downarrow \uparrow \downarrow \uparrow$ & 127.29 & $\left(\ln \frac{32}{3\pi}\right)(1+3\lambda)\tau$ & 115.18 & 9.51\% & $(1+4\lambda)\tau_0$ & 153.75  & 20.79\%\\
%\hline
%\end{tabular}
%\end{center}
%\end{table*}


\subsection{Discussion on synchronization problems}
\label{sec:sync}

In previous subsections, we assume simultaneous transitions on all the wires. However, for global buses where buffer insertion techniques are usually used to reduce their delay \cite{Tsa06}, simultaneous signal transitions on the bus cannot be guaranteed. Our derived models do not work for buses with synchronization problems.
In the following, we briefly discuss the synchronization problems and conclude with insights on the delay changes of interconnects with synchronization problems and impacts on the CAC designs.

Based on our three-wire and five-wire models, we observe \textbf{two possible scenarios} with regard to the impact of synchronization problems on the delay. When the time differences are relatively small, the delay is increased only by the time differences. When the time differences are sufficiently large, they can change the worst delay of a class to a different class. For instance, the delays of the transition patterns in $0C$ and $1C$ may be increased to those of $2C$ when the time differences are large enough, and similarly $2C$ to $3C$. This is consistent with the observation in~\cite{Dua04}. On the other hand, the delays of the transition patterns in $3C$ may decrease to those of $2C$ class when the time differences are large enough. Intuitively, this is because large time differences change the intended transition patterns into different patterns.
As observed above, depending on the severity of the synchronization problems, the effectiveness of CACs is affected to a varying extent. Furthermore, the sensitiveness to time differences varies with CACs.

%Our delay models also have significant ramification on the design of CACs. First, our delay models directly impact the selection of existing CACs in the presence of synchronization problems by  clearly quantifying the impact of synchronization problems on the worst delays of CACs. As observed above, depending on the severity of the synchronization problems, the effectiveness of CACs is affected to a varying extent. Furthermore, the sensitiveness to time differences varies with CACs. Hence, our delay models help designers to select the appropriate CACs based on expected time differences.
%More importantly, our delay models lead to more efficient CACs. Our delay models presented in this paper have used the same classification of transition patterns as the model in \cite{Sot01}. In a separate work \cite{SWY_sips11_CAC,SWY_J11_CAC}, using our delay models we propose a different classification of transition patterns and more efficient CACs.



\section{Performance evaluation}\label{sec:simulation}
We evaluate the performance of our delay models, and compare it with that of the model in \cite{Sot01} in three scenarios. First, since our delay models focus on three and five adjacent wires, we consider three- and five-wire buses. This scenario is also motivated by partial coding schemes (see, e.g., \cite{Dua01}, \cite{Vic01}, and \cite{Sri07}), which divide a wide bus into sub-buses with a few wires and separate them by shielding wires.
The second scenario is buses with more than five wires. We have run extensive simulations on buses with an odd number of wires (up to 33 wires). Our conclusions are the same regardless of the number of wires. For brevity, we present our simulation results for 17- and 33-wire buses.
In the first two scenarios, we focus on the worst-case delays of the middle wires. To characterize the whole bus transitions, our five-wire model can be applied to all wires to approximate their delays with higher accuracy.
In the third scenario, we assume the transition patterns are limited to those of CACs and consider the worst-case delays for all wires of an 8-wire bus.


\begin{figure}[!tb]
\begin{minipage}[b]{1.0\linewidth}
  \centering
 \centerline{\epsfig{figure=interconnect,width=7.5cm}}
\end{minipage}
\caption{Interconnect structure.}
\label{fig:interconnect}
\end{figure}

All the simulation results in this paper are obtained by the following setup. The simulation is based on a 45nm technology with 10 metal layers~\cite{FreePDK45}. The global buses are routed in the top two metal layers, 10 and 9, with a ground metal layer 8 down below as shown in Fig.~\ref{fig:interconnect}.
We consider metal layer 10 for all buses, since the crosstalk is more serious than that of metal layer 9.
The bus parameters are obtained by structure 1 in \cite{PTM} and summarized in Table~\ref{tab:parameter}, where $K_{\textrm{ILD}}$ is the permittivity of the dielectric between metals.
Since the model in~\cite{Sot01} does not account for the loading capacitance, we assume $C_L = 0$ fF for simulations in comparison with the model in~\cite{Sot01}. We also simulate 17- and 33-wire buses with $C_L = 100$ fF, which represents the loading capacitance induced by a 400 times inverter.
The coupling factor is given by $\lambda = \frac{c_c}{c} \doteq 12.2$.
For inputs with $t_r = 10$ ps, inductance effect is negligible when 1.3 mm $< L <$ 66.7 mm. All the buses for simulation have a length of 5 mm and the inductance effect is not considered in this work. The buses are divided into 100 sections as shown in Fig.~\ref{fig:3bus} to characterize the distributed RC model. The simulation results are obtained from HSPICE.

%We choose $\lambda=10$, which is typical for a 0.1$\mu$m process \cite{Dua04}. The simulation results are obtained from HSPICE on a 5mm long bus. The parasitic parameters are given by \cite{Kha01}, and the parameter $\tau_0=\frac{rcL^2}{2}$ is approximately 3.75ps. Though the assumed process is somewhat outdated, we have also tried other process technologies with different values for $\lambda$ and $\tau_0$. Our main conclusion, our delay models have better accuracy than the model in \cite{Sot01},  remains the same for all process technologies. Since we care about the delay on the bus, the delay introduced by other parts is ignored. For this reason, no buffer is used.




\subsection{Three-wire and five-wire buses}
For a three-wire bus, the simulated delays are compared with the delays by our model and the model in \cite{Sot01} for all classes in Table~\ref{tab:1}, where $T_d$ denotes the simulated worst delay of wire 2, $T^{iC}_3$ the approximate delay for $iC$ pattern by our three-wire model, and $T_2$ by the model in \cite{Sot01}. The error percentages of our model and the model in \cite{Sot01} are also shown in Table~\ref{tab:1}. For all five classes of transition patterns, the \textbf{maximum} and \textbf{minimum} errors by our model are only 3.14\% and 0.47\%, respectively, as opposed to 891.90\% and 34.38\% by the model in \cite{Sot01}, respectively. As Table~\ref{tab:1} shows, our model is much more accurate than the model in \cite{Sot01} for all patterns in a three-wire bus. We remark that the delay by our model for the $1C$ pattern, $\left(\ln{\frac{16}{\pi}}\right)\tau$, does not depend on $\lambda$.


\begin{table}
\caption{Comparison of simulated delays, delays of our three-wire model and the model in \cite{Sot01}. All the delays are in $\mathrm{ps}$.}\label{tab:1}
\begin{center}
\begin{tabular}{|r|c|c|c|c|c|c|}
\hline
\multirow{2}{*}{$iC$}& Worst & Sim. & \multicolumn{2}{|c|}{Our model} & \multicolumn{2}{|c|}{\cite{Sot01}}\\
\cline{3-7} & pattern & $T_d$ & $T^{iC}_3$ & $\frac{|T^{iC}_3-T_d|}{T_d}$ & $T_2$ &  $\frac{|T_2-T_d|}{T_d}$\\
\hline
$0C$ & $\uparrow \uparrow \uparrow$ & 3.96 & 4.04 & 2.02\% & 5.55 & 40.15\%\\
\hline
$1C$ & $\uparrow \uparrow$- & 7.41 & 7.56 & 2.02\% & 73.50  & 891.90\%\\
\hline
$2C$ & -$\uparrow$- & 72.28 & 74.55 &  3.14\% & 141.45 & 95.70\%\\
\hline
$3C$ & $\downarrow \uparrow$- & 150.74 & 152.24 &  1.00\% & 209.40 & 38.91\%\\
\hline
$4C$ & $\downarrow \uparrow \downarrow$ & 206.40 & 207.36 & 0.47\% & 277.35  & 34.38\%\\
\hline
\end{tabular}
\end{center}
\end{table}

\begin{table}
\caption{Comparison of simulated delays, delays of our five-wire model and the model in \cite{Sot01}. All the delays are in $\mathrm{ps}$.}\label{tab:2}
\begin{center}
\begin{tabular}{|r|c|c|c|c|c|c|}
\hline
\multirow{2}{*}{$iC$}& Worst & Sim. & \multicolumn{2}{|c|}{Our model} & \multicolumn{2}{|c|}{\cite{Sot01}}\\
\cline{3-7} & pattern & $T_d$ & $T^{iC}_5$ & $\frac{|T^{iC}_5-T_d|}{T_d}$ & $T_3$ &  $\frac{|T_3-T_d|}{T_d}$\\
\hline
$0C$ & $\downarrow \uparrow \uparrow \uparrow \downarrow$ & 35.30 & 23.15 & 34.41\% & 5.55 & 84.28\%\\
\hline
$1C$ & $\downarrow$-$\uparrow \uparrow \downarrow$ & 63.09 & 62.09 & 1.59\% & 73.50  & 16.50\%\\
\hline
$2C$ & $\downarrow$-$\uparrow$-$\downarrow$ & 98.39 & 106.43 &  8.17\% & 141.45 & 43.76\%\\
\hline
$3C$ & $\uparrow$-$\uparrow \downarrow \uparrow$ & 134.19 & 152.24 &  13.45\% & 209.40 & 56.05\%\\
\hline
$4C$ & $\uparrow \downarrow \uparrow \downarrow \uparrow$ & 218.91 & 207.36 & 5.28\% & 277.35  & 26.70\%\\
\hline
\end{tabular}
\end{center}
\end{table}


%\begin{table*}
%\caption{Comparison of simulated delays and delays given by our five-wire model and the model in \cite{Sot01} for wire 9 in a 17-wire bus. All the delays are in $\mathrm{ps}$.}\label{tab:5}
%\begin{center}
%\begin{tabular}{|r|c|c|c|c|c|c|}
%\hline
%\multirow{2}{*}{$iC$} & Worst patterns & Sim. & \multicolumn{2}{c|}{Our model} & \multicolumn{2}{c|}{\cite{Sot01}}\\
%\cline{3-7} & with respect to our assumptions & $T_d$ & $T^{iC}_5$ & $\frac{|T^{iC}_5-T_d|}{T_d}$ & $T_9$ &  $\frac{|T_9-T_d|}{T_d}$\\
%\hline
%$0C$ & $\uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow (\uparrow \uparrow \uparrow) \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow$ & 42.17 &  23.15 & 45.10\% &  5.55  & 86.84\%\\
%\hline
%$1C$ & $\uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow (\uparrow \uparrow \mbox{-}) \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow$ & 67.50 & 62.09 & 8.01\% & 73.50  & 8.89\%\\
%\hline
%$2C$ & $\downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow (\mbox{-} \uparrow \mbox{-}) \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow$ & 112.82 & 106.43 &  5.66\% & 141.45 & 25.38\%\\
%\hline
%$3C$ & $\downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \downarrow (\downarrow \uparrow \mbox{-}) \downarrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow$ & 165.44 & 152.24 &  7.98\% & 209.40 & 26.57\%\\
%\hline
%$4C$ & $\uparrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow (\downarrow \uparrow \downarrow) \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \uparrow$ & 228.46 & 207.36 & 9.24\% & 277.35  & 21.40\%\\
%\hline
%\end{tabular}
%\end{center}
%\end{table*}

%\begin{table*}
%\caption{Comparison of simulated delays and delays given by our five-wire model and the model in \cite{Sot01} for wire 9 in a 17-wire bus. All the delays are in $\mathrm{ps}$.}\label{tab:5}
%\begin{center}
%\begin{tabular}{|r|c|c|c|c|c|c|c|c|c|}
%\hline
%\multirow{3}{*}{$iC$} &  & \multicolumn{5}{c|}{$C_L = 0$fF} & \multicolumn{3}{|c|}{$C_L = 100$fF}\\
%\cline{3-10}
%& Worst patterns & Sim. & \multicolumn{2}{c|}{Our model} & \multicolumn{2}{c|}{\cite{Sot01}} & Sim. & \multicolumn{2}{c|}{Our model}\\
%\cline{3-10}
%& with respect to our assumptions & $T_d$ & $T^{iC}_5$ & $\frac{|T^{iC}_5-T_d|}{T_d}$ & $T_9$ &  $\frac{|T_9-T_d|}{T_d}$ & $T_d$ & $T^{iC}_5$ & $\frac{|T^{iC}_5-T_d|}{T_d}$\\
%\hline
%$0C$ & $\uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow (\uparrow \uparrow \uparrow) \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow$ & 42.17 &  23.15 & 45.10\% &  5.55  & 86.84\% & 50.16 & 25.11 & 49.94\%\\
%\hline
%$1C$ & $\uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow (\uparrow \uparrow \mbox{-}) \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow$ & 67.50 & 62.09 & 8.01\% & 73.50  & 8.89\% & 76.20 & 67.35 & 11.61\%\\
%\hline
%$2C$ & $\downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow (\mbox{-} \uparrow \mbox{-}) \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow$ & 112.82 & 106.43 &  5.66\% & 141.45 & 25.38\% & 118.16 & 123.46 & 4.49\%\\
%\hline
%$3C$ & $\downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \downarrow (\downarrow \uparrow \mbox{-}) \downarrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow$ & 165.44 & 152.24 &  7.98\% & 209.40 & 26.57\% & 177.40 & 164.62 & 7.20\%\\
%\hline
%$4C$ & $\uparrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow (\downarrow \uparrow \downarrow) \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \uparrow$ & 228.46 & 207.36 & 9.24\% & 277.35  & 21.40\% & 235.53 & 224.41 & 4.72\%\\
%\hline
%\end{tabular}
%\end{center}
%\end{table*}


\begin{table*}
\caption{Comparison of simulated delays and delays given by our five-wire model and the model in \cite{Sot01} for wire 9 in a 17-wire bus with $C_L = 0$ $\mathrm{fF}$. All the delays are in $\mathrm{ps}$.}\label{tab:5}
\begin{center}
\begin{tabular}{|c|c|c|c|c|c|c|}
\hline
\multirow{3}{*}{$iC$} & Worst patterns & Sim. & \multicolumn{2}{c|}{Our model} & \multicolumn{2}{c|}{\cite{Sot01}} \\
\cline{3-7}
& via Alg.~\ref{alg:findworst} & $T_d$ & $T^{iC}_5$ & $\frac{|T^{iC}_5-T_d|}{T_d}$ & $T_9$ &  $\frac{|T_9-T_d|}{T_d}$ \\
\hline
$0C$ & $\uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow (\uparrow \uparrow \uparrow) \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow$ & 42.17 &  23.15 & 45.10\% &  5.55  & 86.84\% \\
\hline
$1C$ & $\uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow (\uparrow \uparrow \mbox{-}) \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow$ & 67.50 & 62.09 & 8.01\% & 73.50  & 8.89\% \\
\hline
$2C$ & $\downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow (\mbox{-} \uparrow \mbox{-}) \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow$ & 112.82 & 106.43 &  5.66\% & 141.45 & 25.38\% \\
\hline
$3C$ & $\downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \downarrow (\downarrow \uparrow \mbox{-}) \downarrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow$ & 165.44 & 152.24 &  7.98\% & 209.40 & 26.57\% \\
\hline
$4C$ & $\uparrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow (\downarrow \uparrow \downarrow) \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \uparrow$ & 228.46 & 207.36 & 9.24\% & 277.35  & 21.40\% \\
\hline
\end{tabular}
\end{center}
\end{table*}

%\begin{table*}
%\caption{Comparison of simulated delays and delays given by our five-wire model and the model in \cite{Sot01} for wire 9 in a 17-wire bus. All the delays are in $\mathrm{ps}$.}\label{tab:5}
%\begin{center}
%\begin{tabular}{|r|c|c|c|c|c|c|c|c|c|}
%\hline
%\multirow{3}{*}{$iC$} &  & \multicolumn{5}{c|}{$C_L = 0$fF} & \multicolumn{3}{|c|}{$C_L = 10$fF}\\
%\cline{3-10}
%& Worst patterns & Sim. & \multicolumn{2}{c|}{Our model} & \multicolumn{2}{c|}{\cite{Sot01}} & Sim. & \multicolumn{2}{c|}{Our model}\\
%\cline{3-10}
%& with respect to our assumptions & $T_d$ & $T^{iC}_5$ & $\frac{|T^{iC}_5-T_d|}{T_d}$ & $T_9$ &  $\frac{|T_9-T_d|}{T_d}$ & $T_d^\prime$ & $T^{iC\prime}_5$ & $\frac{|T^{iC\prime}_5-T_d|}{T_d^\prime}$\\
%\hline
%$0C$ & $\uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow (\uparrow \uparrow \uparrow) \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow$ & 42.17 &  24.08 & 42.90\% &  5.55  & 86.84\% & 42.88 & 24.08 & 43.84\%\\
%\hline
%$1C$ & $\uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow (\uparrow \uparrow \mbox{-}) \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow$ & 67.50 & 64.57 & 4.34\% & 73.50  & 8.89\% & 68.56 & 64.57 & 5.82\%\\
%\hline
%$2C$ & $\downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow (\mbox{-} \uparrow \mbox{-}) \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow$ & 112.82 & 109.67 &  2.79\% & 141.45 & 25.38\% & 113.42 & 111.42 & 1.76\%\\
%\hline
%$3C$ & $\downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow (\downarrow \uparrow \mbox{-}) \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow$ & 155.18 & 156.34 &  0.75\% & 209.40 & 34.94\% & 154.93 & 157.62 & 1.74\%\\
%\hline
%$4C$ & $\uparrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow (\downarrow \uparrow \downarrow) \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \uparrow$ & 228.46 & 213.67 & 6.47\% & 277.35  & 21.40\% & 229.30 & 215.43 & 6.05\%\\
%\hline
%\end{tabular}
%\end{center}
%\end{table*}

%\begin{table*}[t]
%\caption{Comparison of simulated delays and delays given by our five-wire model and \cite{Sot01} for wire 17 in a 33-wire bus. All the delays are in $\mathrm{ps}$.}\label{tab:6}
%\begin{center}
%\begin{tabular}{|r|c|c|c|c|c|c|}
%\hline
%\multirow{2}{*}{$iC$} & Worst patterns & Sim. & \multicolumn{2}{c|}{Our model} & \multicolumn{2}{c|}{\cite{Sot01}}\\
%\cline{3-7} & with respect to our assumptions & $T_d$ & $T^{iC}_5$ & $\frac{|T^{iC}_5-T_d|}{T_d}$ & $T_{17}$ &  $\frac{|T_{17}-T_d|}{T_d}$\\
%\hline
%$0C$ & $\downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow (\uparrow \uparrow \uparrow) \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow  \downarrow \downarrow$ & 42.27 &  23.15 & 45.23\% & 5.55  & 86.87\%\\
%\hline
%$1C$ & $\downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow (\mbox{-}\uparrow\uparrow) \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow$ & 68.30 & 62.09 & 9.09\% & 73.50  & 7.61\%\\
%\hline
%$2C$ & $\uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow (\mbox{-} \uparrow \mbox{-}) \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow$ & 113.16 & 106.43 &  5.95\% & 141.45 & 25.00\%\\
%\hline
%$3C$ & $\downarrow \downarrow \uparrow \uparrow \uparrow \uparrow  \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \downarrow (\mbox{-} \uparrow \downarrow) \downarrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow  \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow$ & 165.57 & 152.24 &  8.05\% & 209.40 & 26.47\%\\
%\hline
%$4C$ & $\downarrow \downarrow \downarrow\downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow (\downarrow \uparrow \downarrow) \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow$  & 229.02 & 207.36 & 9.46\% & 277.35 & 21.10\%\\
%\hline
%\end{tabular}
%\end{center}
%\end{table*}


%\begin{table*}
%\caption{Comparison of simulated delays and delays given by our five-wire model and \cite{Sot01} for wire 17 in a 33-wire bus. All the delays are in $\mathrm{ps}$.}\label{tab:6}
%\begin{center}
%\begin{tabular}{|r|c|c|c|c|c|c|c|c|c|}
%\hline
%\multirow{3}{*}{$iC$} &  & \multicolumn{5}{c|}{$C_L = 0$fF} & \multicolumn{3}{|c|}{$C_L = 100$fF}\\
%\cline{3-10}
%& Worst patterns & Sim. & \multicolumn{2}{c|}{Our model} & \multicolumn{2}{c|}{\cite{Sot01}} & Sim. & \multicolumn{2}{c|}{Our model}\\
%\cline{3-10}
%& with respect to our assumptions & $T_d$ & $T^{iC}_5$ & $\frac{|T^{iC}_5-T_d|}{T_d}$ & $T_{17}$ &  $\frac{|T_{17}-T_d|}{T_d}$ & $T_d$ & $T^{iC}_5$ & $\frac{|T^{iC}_5-T_d|}{T_d}$\\
%\hline
%$0C$ & $\downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow (\uparrow \uparrow \uparrow) \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow  \downarrow \downarrow$ & 42.27 &  23.15 & 45.23\% & 5.55  & 86.87\% & 50.16 & 25.11 & 50.06\% \\
%\hline
%$1C$ & $\downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow (\mbox{-}\uparrow\uparrow) \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow$ & 68.30 & 62.09 & 9.09\% & 73.50  & 7.61\% & 76.11 & 67.35 & 11.51\% \\
%\hline
%$2C$ & $\uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow (\mbox{-} \uparrow \mbox{-}) \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow$ & 113.16 & 106.43 &  5.95\% & 141.45 & 25.00\% & 118.27 & 123.46 & 4.39\% \\
%\hline
%$3C$ & $\downarrow \downarrow \uparrow \uparrow \uparrow \uparrow  \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \downarrow (\mbox{-} \uparrow \downarrow) \downarrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow  \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow$ & 165.57 & 152.24 &  8.05\% & 209.40 & 26.47\% & 177.28 & 164.62 & 7.14\% \\
%\hline
%$4C$ & $\downarrow \downarrow \downarrow\downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow (\downarrow \uparrow \downarrow) \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow$  & 229.02 & 207.36 & 9.46\% & 277.35 & 21.10\% & 235.95 & 224.41 & 4.89\% \\
%\hline
%\end{tabular}
%\end{center}
%\end{table*}

\begin{table*}
\caption{Comparison of simulated delays and delays given by our five-wire model and \cite{Sot01} for wire 17 in a 33-wire bus with $C_L = 0$ $\mathrm{fF}$. All the delays are in $\mathrm{ps}$.}\label{tab:6}
\begin{center}
\begin{tabular}{|c|c|c|c|c|c|c|}
\hline
\multirow{2}{*}{$iC$} & Worst patterns & Sim. & \multicolumn{2}{c|}{Our model} & \multicolumn{2}{c|}{\cite{Sot01}} \\
\cline{3-7}
& via Alg.~\ref{alg:findworst} & $T_d$ & $T^{iC}_5$ & $\frac{|T^{iC}_5-T_d|}{T_d}$ & $T_{17}$ &  $\frac{|T_{17}-T_d|}{T_d}$ \\
\hline
$0C$ & $\downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow (\uparrow \uparrow \uparrow) \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow  \downarrow \downarrow$ & 42.27 &  23.15 & 45.23\% & 5.55  & 86.87\% \\
\hline
$1C$ & $\downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow (\mbox{-}\uparrow\uparrow) \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow$ & 68.30 & 62.09 & 9.09\% & 73.50  & 7.61\% \\
\hline
$2C$ & $\uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow (\mbox{-} \uparrow \mbox{-}) \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow$ & 113.16 & 106.43 &  5.95\% & 141.45 & 25.00\% \\
\hline
$3C$ & $\downarrow \downarrow \uparrow \uparrow \uparrow \uparrow  \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \downarrow (\mbox{-} \uparrow \downarrow) \downarrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow  \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow$ & 165.57 & 152.24 &  8.05\% & 209.40 & 26.47\% \\
\hline
$4C$ & $\downarrow \downarrow \downarrow\downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow (\downarrow \uparrow \downarrow) \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow$  & 229.02 & 207.36 & 9.46\% & 277.35 & 21.10\% \\
\hline
\end{tabular}
\end{center}
\end{table*}


\begin{table*}
\caption{Comparison of simulated delays and delays given by our five-wire model focusing on the middle wire in a 17-wire and a 33-wire buses with $C_L = 100$ $\mathrm{fF}$. All the delays are in $\mathrm{ps}$.}\label{tab:100fF}
\begin{center}
\begin{tabular}{|c|c|c|c|c|c|c|c|c|}
\hline
\multirow{2}{*}{$iC$}& Worst 17-wire patterns & Sim. & \multicolumn{2}{c|}{Our model} & Worst 33-wire patterns & Sim. & \multicolumn{2}{c|}{Our model} \\
\cline{3-5}\cline{7-9}
& via Alg.~\ref{alg:findworst} & $T_d$ & $T^{iC}_5$ & $\frac{|T^{iC}_5-T_d|}{T_d}$ & via Alg.~\ref{alg:findworst} & $T_d$ & $T^{iC}_5$ & $\frac{|T^{iC}_5-T_d|}{T_d}$\\
\hline
$0C$ & $\uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow (\uparrow \uparrow \uparrow) \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow$ & 50.75 &  25.11 & 50.52\% & $\downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow (\uparrow \uparrow \uparrow) \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow  \uparrow \downarrow$ & 50.78 &  25.11 & 50.55\% \\
\hline
$1C$ & $\uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow (\uparrow \uparrow \mbox{-}) \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow$ & 76.42 & 67.35 & 11.87\% & $\downarrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow (\mbox{-}\uparrow\uparrow) \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow$ & 76.43 & 67.35 & 11.88\% \\
\hline
$2C$ & $\uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow (\mbox{-} \uparrow \mbox{-}) \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow$ & 118.92 & 123.46 &  3.82\% & $\uparrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow (\mbox{-} \uparrow \mbox{-}) \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \uparrow$ & 119.21 & 123.46 &  3.57\% \\
\hline
$3C$ & $\downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow (\downarrow \uparrow \mbox{-}) \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow$ & 177.71 & 164.62 &  7.37\% & $\downarrow \downarrow \uparrow \uparrow \downarrow \downarrow  \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow (\mbox{-} \uparrow \downarrow) \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow  \downarrow \downarrow \uparrow \uparrow \downarrow \downarrow$ & 177.74 & 164.62 &  7.38\% \\
\hline
$4C$ & $\uparrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow (\downarrow \uparrow \downarrow) \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \uparrow$ & 236.18 & 224.41 & 4.98\% & $\downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow (\downarrow \uparrow \downarrow) \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow$  & 236.67 & 224.41 & 5.18\% \\
\hline
\end{tabular}
\end{center}
\end{table*}




For a five-wire bus, the worst delays of all classes of transition patterns based on our five-wire model are compared with those of the model in \cite{Sot01} as well as the simulated delays by HSPICE in Table~\ref{tab:2}, where $T_d$ denotes the simulated worst-case delay of wire 3 for all $iC$ patterns, $T^{iC}_5$ the approximate delay for $iC$ pattern by our five-wire model, and $T_3$ by the model in \cite{Sot01}. The error percentages of our model and the model in \cite{Sot01} are shown in Table~\ref{tab:2}. For a five-wire bus the \textbf{maximum} and \textbf{minimum} errors by our model are 34.41\% and 1.59\%, respectively, in comparison to 84.28\% and 16.50\% by the model in \cite{Sot01}, respectively.
As Table~\ref{tab:2} shows, our five-wire model is more accurate than the model in \cite{Sot01} for all patterns in a five-wire bus. In particular, although the delays in the model in \cite{Sot01} were claimed to be upper bounds on the actual delays, our simulation results in Table~\ref{tab:2} show that this claim is invalid for the $0C$ patterns. In \cite{Dua04}, the author proposed a method which achieves a delay of $\tau_0$ by surrounding each data wire with two shield wires with the same transition. Since the transition patterns for each data wire are always in $0C$ class, the delays of the data wires are $\tau_0$ according to the model in \cite{Sot01}. In contrast, the delay for the data wires can be as large as $0.165(1+3\lambda)\tau_0$ by our model; When $\lambda$ is large, the model in \cite{Sot01} severely underestimates the delay, while our model is more accurate.

%\subsection{five-wire model extension}
%It is highly desirable to give an accurate yet simple delay model to approximate the delays of a general bus. Our 5-wire model has higher accuracy than the model in \cite{Sot01}. Furthermore, the pattern classification is still based on only 3 wires.

\subsection{17-wire and 33-wire buses}
We next compare our five-wire model with the model in \cite{Sot01} for 17- and 33-wire buses. With a 17-wire bus, we focus on the middle wire (wire 9). We still classify the transition patterns according to the transitions of the middle three wires (wires 8, 9, and 10).
Since it is time consuming to identify the transition patterns with the longest delay in each class, we make one assumption about the patterns with the longest delay in each class. For any two wires symmetric to wire 9 (wire $i$ and wire $18$-$i$, $i \in \{1,2,\cdots, 8\}$), there are nine possible patterns, $\uparrow \uparrow$, $\downarrow \downarrow$, - -, $\uparrow$-, -$\uparrow$, $\downarrow$-, -$\downarrow$, $\uparrow \downarrow$, and $\downarrow \uparrow$. For patterns in opposite direction, we assume the influences of the two wires will cancel out because of symmetry. For other patterns, if the upward transition of one wire increases the delay, we see that $\uparrow \uparrow$ has greater delay than $\uparrow$- or -$\uparrow$. Similarly, if the downward transition increases the delay, the pattern $\downarrow \downarrow$ has greater delay than $\downarrow$- or -$\downarrow$. So we assume that the longest delay happens when two symmetric wires have either $\uparrow \uparrow$ or $\downarrow \downarrow$ transitions.

Based on this assumption, we search all possible symmetric transition patterns to find the worst-case patterns in each class, which
are listed in the second column of Table~\ref{tab:5}, where the pattern on wires 8, 9, and 10 are shown in the parenthesis. The simulated worst-case delays for all $iC$, denoted by $T_d$, are compared with the delays by our five-wire model and the model in \cite{Sot01} in Table~\ref{tab:5}. The error percentage of our model and the model in \cite{Sot01}  are also shown in Table~\ref{tab:5}. For all five classes, the \textbf{maximum} and \textbf{minimum} errors by our model are only 45.10\% and 5.66\%, respectively, as opposed to 86.84\% and 8.89\% by the model in \cite{Sot01}, respectively. For all classes except $1C$, our five-wire model outperforms the model in \cite{Sot01}. The model in \cite{Sot01} also has a large error percentage for $0C$.




With a 33-wire bus, we focus on the delay of the middle wire (wire 17). Since there are $3^{33}$ transition patterns, it is infeasible to search all possible symmetric transitions as before to find the worst-case patterns. We make the following three assumptions: (1) The worst patterns in each classes are symmetric; (2) The closer the wire gets to the middle wire, the greater the coupling on the settling of the middle wire; (3) We initialize the middle three wires to a pattern in $iC$, and initialize all other wires with opposite transitions to the middle wire. Based on these three assumptions, we use Alg.~\ref{alg:findworst} to find the patterns with largest delays. We denote by $P_i$ the updated transition pattern of an $m$-wire bus after the $i$-th iteration of Alg.~\ref{alg:findworst}, where $m$ is odd. Alg.~\ref{alg:findworst} can greatly reduce the simulation time for identifying the worst-case patterns. For instance, the worst-case patterns for an $33$-wire bus can be identified by simulating only $5 \times 15 = 75$ transition patterns.

%\begin{algorithm}
%\SetAlgoLined
%\KwIn{$m$-wire bus}
%\KwOut{Worst-case transition pattern for wire $\frac{m+1}{2}$}
%Initialization: $P_0$ is initialized with transitions opposite to wire $\frac{m+1}{2}$, except for wires $\frac{m-1}{2}$, $\frac{m+1}{2}$, and $\frac{m+3}{2}$\;
%$i=0$\;
%\Repeat{$P_{i-1} = P_i$}
%{
%\For{$j$ = $\frac{m-3}{2}$ to 1}{
%Flip the transition of wires $j$ and ($m+1-j$) in $P_i$\;
%\If{the delay of wire $\frac{m+1}{2}$ increases}{
%Keep the changes\;
%}
%\Else{
%Reverse the changes\;
%}
%}
%i++\;
%Update $P_{i}$ with the current pattern\;
%}
%\caption{The algorithm for identifying the worst-case pattern, with respect to the three assumptions, in an $m$-wire bus.}
%\label{alg:findworst}
%\end{algorithm}

\begin{algorithm}[!tp]
  \caption{The algorithm for identifying the worst-case pattern, with respect to the three assumptions, in an $m$-wire bus.}
  \begin{algorithmic}
    \REQUIRE $m$-wire bus;
    \STATE \textbf{Initialize}: $P_0$ is initialized with transitions opposite to wire $\frac{m+1}{2}$, except for wires $\frac{m-1}{2}$, $\frac{m+1}{2}$, and $\frac{m+3}{2}$;
    \STATE $i=0$;
    \REPEAT
    \FOR{$j$ = $\frac{m-3}{2}$ to 1}
    \STATE Flip the transition of wires $j$ and ($m+1-j$) in $P_i$;
    \IF{the delay of wire $\frac{m+1}{2}$ increases}
    \STATE Keep the changes;
    \ELSE
    \STATE Reverse the changes;
    \ENDIF
    \ENDFOR
    \STATE $i=i+1$;
    \STATE Update $P_{i}$ with the current pattern;
    \UNTIL{$P_{i-1} = P_i$}
    \RETURN Worst-case transition pattern for wire $\frac{m+1}{2}$;
  \end{algorithmic}
  \label{alg:findworst}
\end{algorithm}


We note that the one assumption about the worst-case patterns for 17-wire buses and the three assumptions about 33-wire buses are made in order to reduce the complexity of finding the worst-case patterns. We did verify our three assumptions about 33-wire buses over 9- and 11-wire buses: the worst cases for all the classes based on Alg.~\ref{alg:findworst} are indeed the worst cases by exhaustive search.
This also verifies the assumption for 17-wire buses, since it is one of the three assumptions for 33-wire buses.
For instance, the worst-case $2C$ pattern of a 11-wire bus is given by $\u\u\u\d$-$\u$-$\d\u\u\u$ with exhaustive search. In Alg.~\ref{alg:findworst}, starting from $\d\d\d\d$-$\u$-$\d\d\d\d$, the worst-case pattern is found via the order: $\d\d\d\d$-$\u$-$\d\d\d\d$ $\Longrightarrow$ $\d\d\u\d$-$\u$-$\d\u\d\d$ $\Longrightarrow$ $\d\u\u\d$-$\u$-$\d\u\u\d$ $\Longrightarrow$ $\u\u\u\d$-$\u$-$\d\u\u\u$.
Unfortunately, it is difficult to verify Alg.~\ref{alg:findworst}, even for one case, for 17- or 33-wire buses, because the complexity would be prohibitive. For instance, for each class focusing on the middle wire, there are $3^{14}=4782969$ possible patterns for a 17-wire bus (and $3^{30}\doteq 2.06\times 10^{14}$ for a 33-wire bus), and it takes about 166 days to simulate these cases.




%\begin{table*}
%\caption{Comparison of simulated delays and delays given by our five-wire model and \cite{Sot01} for wire 17 in a 33-wire bus ($\tau_0=3.75\mathrm{ps}$,~$\tau=\frac{8}{\pi^2}\tau_0$, and $\lambda=10$). All the delays are in $\mathrm{ps}$. }\label{tab:6}
%\begin{center}
%\begin{tabular}{|r|c|c|c|c|c|c|}
%\hline
%\multirow{2}{*}{$iC$} & Worst patterns & Sim. & \multicolumn{2}{c|}{Our model} & \multicolumn{2}{c|}{\cite{Sot01}}\\
%\cline{3-7} & with respect to our assumptions & $T_d$  & $T^{iC}_5$& $\frac{|T^{iC}_5-T_d|}{T_d}$ & $T_{17}$ &  $\frac{|T_{17}-T_d|}{T_d}$\\
%\hline
%$0C$ & $\downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow (\uparrow \uparrow \uparrow) \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow  \downarrow \downarrow$ & 25.16 &  19.18 & 23.77\% & 3.75  & 85.10\%\\
%\hline
%$1C$ & $\downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow (\mbox{-}\uparrow\uparrow) \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow \downarrow$ & 39.63 & 34.99 & 11.71\% & 41.25  & 4.09\%\\
%\hline
%$2C$ & $\uparrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow (\mbox{-} \uparrow \mbox{-}) \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \uparrow$ & 65.98 & 59.46 &  9.88\% & 78.75 & 19.35\%\\
%\hline
%$3C$ & $\downarrow \downarrow \uparrow \uparrow \uparrow \uparrow  \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow (\mbox{-} \uparrow \downarrow) \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \uparrow  \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow$ & 95.59 & 88.08 &  7.86\% & 116.25 & 21.61\%\\
%\hline
%$4C$ & $\downarrow \downarrow \downarrow\downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow (\downarrow \uparrow \downarrow) \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \uparrow \uparrow \uparrow \uparrow \downarrow \downarrow \downarrow \downarrow \downarrow$  & 130.57 & 115.18 & 11.79\% & 153.75 & 17.75\%\\
%\hline
%\end{tabular}
%\end{center}
%\end{table*}

The worst transition patterns for each class in a 33-wire bus, with respect to the three assumptions above, are listed in the second column of Table~\ref{tab:6}, where the pattern on wires 16, 17, and 18 are shown in the parenthesis.
The simulated worst-case delays of wire 17 for all $iC$ patterns, denoted by $T_d$, are compared with the delays of our five-wire model and the model in \cite{Sot01}. The error percentages of our model and the model in \cite{Sot01} are also shown in Table~\ref{tab:6}. The \textbf{maximum} and \textbf{minimum} errors by our model are only 45.23\% and 5.95\%, respectively, in comparison to 86.87\% and 7.61\% by the model in \cite{Sot01}, respectively. Again, for all classes except $1C$, our five-wire model outperforms the model in \cite{Sot01}. The model in \cite{Sot01} also has a large error percentage for $0C$.

Since our revised models also account for the loading capacitance, we also simulate 17- and 33-wire buses with $C_L = 100$ fF, which represents the loading capacitance induced by a 400 times inverter. The simulated worst-case delays of the middle wire for all $iC$ patterns, denoted by $T_d$, are compared with the delays $T_5^{iC}$ by our five-wire model as shown in Table~\ref{tab:100fF}. The error percentages of our model are also shown in Table~\ref{tab:100fF}. The worst-case patterns are obtained via Alg.~\ref{alg:findworst}. The worst-case patterns are different from those in Tables \ref{tab:5} and \ref{tab:6} due to the varying of the loading capacitances. However, our five-wire model can still approximate the delays with similar error percentages as those in Tables \ref{tab:5} and \ref{tab:6}.


Finally, we remark that the longest delays for each class in Tables \ref{tab:5} and \ref{tab:6} are approximately the same for both 17- and 33-wire buses.
Based on the simulation results of 17- and 33-wire buses, we conjecture that our five-wire model would be more accurate than the model in \cite{Sot01} for buses with any number of wires.

%\begin{table}[t]
%\caption{Comparison of simulated delays and delays given by our five-wire model and \cite{Sot01} for all wire in a 16-wire bus. All the delays are in $\mathrm{ps}$.}\label{tab:16wire}
%\begin{center}
%\begin{tabular}{|c|c|c|c|c|c|c|c|}
%\hline
%$i$ & OLC & FPC& FOC & $i$ & OLC & FPC& FOC\\
%\hline
%1 & 55.97 & 109.18 & 108.39 & 9 & \textbf{56.06} & 106.69 & \textbf{165.04}\\
%\hline
%2 & 34.43 & 104.66 & 160.71 & 10 & 55.68 & 106.73 & 161.07\\
%\hline
%3 & 54.74 & 107.38 & 156.65 & 11 & 54.16 & 108.51 & 163.95\\
%\hline
%4 & 55.30 & 104.56 & 162.43 & 12 & 52.99 & 107.03 & 162.98\\
%\hline
%5 & 52.93 & 107.34 & 161.64 & 13 & 55.24 & 103.79 & 164.06\\
%\hline
%6 & 53.76 & 107.77 & 158.83 & 14 & 54.53 & 107.28 & 155.62\\
%\hline
%7 & 55.51 & 105.93 & 164.47 & 15 & 34.42 & 103.97 & 160.50\\
%\hline
%8 & 55.87 & 106.33 & 161.30 & 16 & 55.97 & \textbf{109.41} & 108.28\\
%\hline
%\hline
%\multicolumn{2}{|c|}{} & \multicolumn{2}{|c|}{OLC} & \multicolumn{2}{|c|}{FPC} & \multicolumn{2}{|c|}{FOC}\\
%\hline
%\multicolumn{2}{|c|}{\cite{Sot01}} & \multicolumn{2}{|c|}{73.50} & \multicolumn{2}{|c|}{141.45} & \multicolumn{2}{|c|}{209.40}\\
%\hline
%\multicolumn{2}{|c|}{$T^{iC}_5$} & \multicolumn{2}{|c|}{62.09} & \multicolumn{2}{|c|}{106.43} & \multicolumn{2}{|c|}{152.24}\\
%\hline
%\end{tabular}
%\end{center}
%\end{table}


%\begin{table}[h]
%\caption{Comparison of simulated delays and delays given by our five-wire model and \cite{Sot01} for all wire in a 16-wire bus ($\tau_0=3.75\mathrm{ps}$,~$\tau=\frac{8}{\pi^2}\tau_0$, and $\lambda=10$). All the delays are in $\mathrm{ps}$.}\label{tab:16wire}
%\begin{center}
%\begin{tabular}{|c|c|c|c|c|c|c|c|}
%\hline
%wire $i$ & OLC & FPC& FOC & wire $i$ & OLC & FPC& FOC\\
%\hline
%1 & \textbf{35.00} & \textbf{66.57} & 64.96 & 9 & 34.35 & 64.50 & 96.39\\
%\hline
%2 & 22.24 & 65.14 & 96.23 & 10 & 34.38 & 64.62 & 96.88\\
%\hline
%3 & 33.86 & 65.84 & 96.46 & 11 & 33.79 & 65.20 & 97.50\\
%\hline
%4 & 34.19 & 63.14 & 97.84 & 12 & 33.10 & 65.33 & 97.50\\
%\hline
%5 & 33.13 & 64.55 & 97.27 & 13 & 34.18 & 63.87 & 97.60\\
%\hline
%6 & 33.80 & 65.40 & 96.80 & 14 & 33.66 & 65.21 & 95.50\\
%\hline
%7 & 34.04 & 64.23 & \textbf{98.06} & 15 & 22.20 & 63.74 & 96.62\\
%\hline
%8 & 33.83 & 64.04 & 97.36 & 16 & 34.73 & 66.50 & 65.85\\
%\hline
%\hline
%\multicolumn{2}{|c|}{} & \multicolumn{2}{|c|}{OLC} & \multicolumn{2}{|c|}{FPC} & \multicolumn{2}{|c|}{FOC}\\
%\hline
%\multicolumn{2}{|c|}{\cite{Sot01}} & \multicolumn{2}{|c|}{41.25} & \multicolumn{2}{|c|}{78.75} & \multicolumn{2}{|c|}{116.25}\\
%\hline
%\multicolumn{2}{|c|}{$T^{iC}_5$} & \multicolumn{2}{|c|}{34.99} & \multicolumn{2}{|c|}{59.46} & \multicolumn{2}{|c|}{88.08}\\
%\hline
%\end{tabular}
%\end{center}
%\end{table}


\subsection{Performance of CACs}\label{sec:simCACs}
In the simulation results above, we assume the transition patterns are arbitrary. Herein, we assume the transition patterns are limited to those of CACs. We evaluate the performance of our delay model for three families of CACs \cite{Dua01,Vic01,Sri07}: {\it one Lambda codes} (OLCs), {\it forbidden pattern codes} (FPCs), and {\it forbidden overlap codes} (FOCs).
Based on our five-wire model, the worst delays of aforementioned CACs are shown in Tables~\ref{tab:5wire}, \ref{tab:wire1}, and \ref{tab:wire2}.
%approximated by $0.384(1+3\lambda) \tau$, $\left(\ln \frac{32}{3\pi}\right)\left(1+\frac{3}{2}\lambda\right)\tau$, and $\left(\ln{\frac{8}{\pi}}\right)(1+3\lambda)\tau$, respectively.
Based on the model in \cite{Sot01}, the worst delays of aforementioned CACs are approximated by $(1+\lambda)\tau_0$, $(1+2\lambda)\tau_0$, and $(1+3\lambda)\tau_0$, respectively.
Since the number of transition patterns is a quadratic function of the number of codewords, it is time-consuming to simulate a large bus to get the worst-case delays on all wires.
Hence, for each CAC, we simulate an 8-wire bus. The numbers of codewords of OLC, FPC, and FOC are given by 16, 68, and 149, respectively. The total numbers of transition patterns for OLC, FPC, and FOC are given by 240, 4556, and 22052, respectively.
%choose 10001 codewords from a 16-bit code book randomly, and they form 10000 transitions.
We obtain by simulation the maximum delays of each wire for all transition patterns. The simulation results are shown in Table~\ref{tab:8wire}, where the delays given by our five-wire model and the model in \cite{Sot01} are also included. Intuitively, the worst-case delays of any two symmetric wires are the same, since the symmetric transition of a valid transition pattern is also valid.
As shown in Table~\ref{tab:8wire}, the simulated delays of symmetric wires are very close.
%Due to the limited number of transition patterns for simulations in an $m$-wire bus, the delays on symmetric wires (wires $i$ and $m-i$) are slightly different.
For OLCs, FPCs, and FOCs, the largest delays are emphasized in boldface. As Table~\ref{tab:8wire} shows,
%the worst delay in each class does not change much compared with the worst delay of the middle wire (wire 9). Our
our delay models are more accurate than the model in \cite{Sot01} for all three families of CACs.


\begin{table}[!t]
\caption{Comparison of simulated delays and delays given by our five-wire model and \cite{Sot01} for all wire in an 8-wire bus, where $T^{iC}_5$, $T^{iC}_{b1}$, and $T^{iC}_{b2}$ denote the delays of wires 3-8, wire 1 ($m$), and wire 2 ($m-1$), respectively. All the delays are in $\mathrm{ps}$.}\label{tab:8wire}
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline
\multirow{2}{*}{wire $i$} & \multicolumn{3}{c|}{Delays}\\
\cline{2-4}
& OLC & FPC& FOC\\
\hline
1 & \textbf{55.36} & \textbf{107.43} & 107.73\\
\hline
2 & 32.20 & 102.71 & 159.65\\
\hline
3 & 51.40 & 106.65 & 154.59\\
\hline
4 & 51.06 & 101.91 & 162.61\\
\hline
5 & 50.79 & 101.89 & \textbf{162.77}\\
\hline
6 & 51.39 & 106.53 & 154.62\\
\hline
7 & 32.46 & 102.72 & 160.61\\
\hline
8 & \textbf{55.36} & 107.39 & 108.88\\
\hline
\hline
\cite{Sot02} & 73.50 & 141.45 & 209.40\\
\hline
$T^{iC}_5$ & 62.09 & 106.43 & 152.24\\
\hline
$T^{iC}_{b1}$ & 53.43 & 98.76 & 98.76 \\
\hline
$T^{iC}_{b2}$ & 42.52 & 102.84 & 157.64\\
\hline
\end{tabular}
\end{center}
\end{table}

%In the preceding simulation results, the coupling factor $\lambda$ is assumed to be 10 for a 0.1-$\mu$m technology. For a given technology, the value of $\lambda$ also depends on many factors, such as the metal layer in which we route the bus, the width of each wire, the spacing between adjacent wires, and the distance to the ground layer. To show the generality of our five-wire model with different $\lambda$, we also evaluate the performance of our delay model for the three families of CACs by varying $\lambda$ from 1 to 10. With a chosen $\lambda$, we choose 1000 transitions for each CAC randomly and obtain by simulation the maximum delays of these transitions. The simulation results are shown in Fig.~\ref{fig:cac}, where the delays given by our five-wire model and the model in \cite{Sot01} are also included. As Fig.~\ref{fig:cac} shows, our five-wire model is more accurate than the model in \cite{Sot01} for all three families of CACs with a $\lambda$ no less than two.
%
%
%
%\begin{figure}[!tb]
%\begin{minipage}[b]{1.0\linewidth}
%  \centering
% \centerline{\epsfig{figure=CACwrtlambda,width=8.5cm}}
%\end{minipage}
%\caption{Plot of delays of OLC, FPC, and FOC with respect to $\lambda$.}
%\label{fig:cac}
%\end{figure}


%\begin{table}[h]
%\caption{Comparison of simulated delays and delays given by our five-wire model and \cite{Sot02} for all wire in a 17-wire bus ($\tau_0=3.75\mathrm{ps}$,~$\tau=\frac{8}{\pi^2}\tau_0$, and $\lambda=10$). All the delays are in $\mathrm{ps}$.}\label{tab:17wire}
%\begin{center}
%\begin{tabular}{|c|c|c|c|c|c|c|c|}
%\hline
%wire $i$ & OLC & FPC& FOC & wire $i$ & OLC & FPC& FOC\\
%\hline
%1 & \textbf{33.96} & 64.31 & 63.00 & 10 & 33.27 & 62.21 & 95.94\\
%\hline
%2 & 21.59 & 62.52 & 95.06 & 11 & 31.92 & 61.10 & 94.74\\
%\hline
%3 & 32.37 & 63.73 & 94.90 & 12 & 32.07 & 61.55 & 94.33\\
%\hline
%4 & 32.40 & 62.14 & 96.56 & 13 & 32.02 & 63.31 & 96.56\\
%\hline
%5 & 32.16 & 63.40 & 94.30 & 14 & 32.97 & 60.22 & \textbf{97.24}\\
%\hline
%6 & 32.49 & 64.63 & 96.99 & 15 & 32.83 & 64.70 & 92.01\\
%\hline
%7 & 32.55 & \textbf{65.00} & 93.69 & 16 & 21.29 & 63.25 & 95.29\\
%\hline
%8 & 32.50 & 62.26 & 93.31 & 17 & 33.61 & 63.52 & 63.83\\
%\cline{1-4}
%9 & 33.18 & 60.74 & 94.93 &&&&\\
%\hline
%\hline
%\multicolumn{2}{|c|}{} & \multicolumn{2}{|c|}{OLC} & \multicolumn{2}{|c|}{FPC} & \multicolumn{2}{|c|}{FOC}\\
%\hline
%\multicolumn{2}{|c|}{\cite{Sot02}} & \multicolumn{2}{|c|}{41.25} & \multicolumn{2}{|c|}{78.75} & \multicolumn{2}{|c|}{116.25}\\
%\hline
%\multicolumn{2}{|c|}{$T^{iC}_5$} & \multicolumn{2}{|c|}{34.99} & \multicolumn{2}{|c|}{59.46} & \multicolumn{2}{|c|}{88.08}\\
%\hline
%\end{tabular}
%\end{center}
%\end{table}

%\begin{table}[h]
%\caption{Comparison of simulated delays and delays given by our five-wire model and \cite{Sot02} for all wire in a 17-wire bus ($\tau_0=3.75\mathrm{ps}$,~$\tau=\frac{8}{\pi^2}\tau_0$, and $\lambda=10$). All the delays are in $\mathrm{ps}$.}\label{tab:17wire}
%\begin{center}
%\begin{tabular}{|c|c|c|c|}
%\hline
%& \multicolumn{3}{c|}{Delays}\\
%\cline{2-4}
%& OLC & FPC& FOC\\
%\hline
%\cite{Sot02} & 41.25 & 78.75 & 116.25\\
%\hline
%$T^{iC}_5$ & 34.99 & 59.46 & 88.08\\
%\hline
%wire $i$ &&&\\
%\hline
%1 & \textbf{33.96} & 64.31 & 63.00\\
%\hline
%2 & 21.59 & 62.52 & 95.06\\
%\hline
%3 & 32.37 & 63.73 & 94.90\\
%\hline
%4 & 32.40 & 62.14 & 96.56\\
%\hline
%5 & 32.16 & 63.40 & 94.30\\
%\hline
%6 & 32.49 & 64.63 & 96.99\\
%\hline
%7 & 32.55 & \textbf{65.00} & 93.69\\
%\hline
%8 & 32.50 & 62.26 & 93.31\\
%\hline
%9 & 33.18 & 60.74 & 94.93\\
%\hline
%10 & 33.27 & 62.21 & 95.94\\
%\hline
%11 & 31.92 & 61.10 & 94.74\\
%\hline
%12 & 32.07 & 61.55 & 94.33\\
%\hline
%13 & 32.02 & 63.31 & 96.56\\
%\hline
%14 & 32.97 & 60.22 & \textbf{97.24}\\
%\hline
%15 & 32.83 & 64.70 & 92.01\\
%\hline
%16 & 21.29 & 63.25 & 95.29\\
%\hline
%17 & 33.61 & 63.52 & 63.83\\
%\hline
%\end{tabular}
%\end{center}
%\end{table}






%\section{Delay model with synchronization problems}
%\label{sec:sync}
%
%In this section, we first describe the synchronization problems, and then modify our three-wire and five-wire models to account for synchronization problems. For simplicity, buffer effects are not considered in this section. We conclude this section with insights on the delay changes of interconnects with synchronization problems and impacts on the CAC designs.
%
%\subsection{Synchronization problems}
%A skew refers to the magnitude of the time differences between the actual transition instants of two adjacent wires. It is of great importance for parallel buses, where more than one bit is sent with a clocking signal. Let $t_i$ denote the time instant of the transition edge for wire $i$, and $T$ denote the clock period. All switching instants for wire $i$ are given by $t_i+lT$, where $l$ is an integer. Then the time difference between two different wires is given by $\Delta_{i,k}=t_i-t_k$. Without loss of generality, we assume all switching time instants are within $T/2$ of each other. Fig.~\ref{fig:3btiming} shows the input signals on a bus with synchronization problems, where $D_i$ denotes the input on the $i$-th wire, and $T$ is the period of the clock. $\Delta_{i-1}$ and $\Delta_{i+1}$ is the time differences with wire $i$ as the reference.
%
%For a bus with $m$ wires, we focus on the time difference between each wire and the middle wire (wire $\frac{m+1}{2})$. If no transition on wire $i$ appears within $T/2$ of the middle wire, there is no synchronization problem and $\Delta_i$ can be any value. For convenience, we simply choose $\Delta_i = 0$. The time difference is defined by
%\begin{equation*}
%\Delta_i=\left\{ \begin{array}{ll}
%t_i-t_{\frac{m+1}{2}}, & \mbox{if there is transition on wire }i;\\
%0, & \mbox{if there is no transition on wire } i.
%\end{array} \right.
%\end{equation*}
%By this definition, $|\Delta_i| \le \frac{T}{2}$, for $i\in\{1,2,\cdots,m\}$. Let $t^{iC}_m$ denote the worst delay of the middle wire (wire $\frac{m+1}{2}$) for all $iC$ patterns \textbf{with} synchronization problems.
%
%\begin{figure}[!tb]
%\begin{minipage}[b]{1.0\linewidth}
%\centering
%\centerline{\epsfig{figure=3bustiming,width=8.5cm}}
%\end{minipage}
%\caption{A bus with synchronization problems.}
%\label{fig:3btiming}
%\end{figure}
%
%
%
%
%\subsection{Three-wire model with synchronization problems}
%\label{sec:sync3}
%Henceforth in the paper, since we care about only the outputs of wires $V_{i}(L, t)$, we use $V_{i}(t)$ for simplicity. Similarly, we use $V^i_j(t)$ instead of $V^i_j(L, t)$. Based on the linear property of the system and our three-wire model in Section~\ref{sec:3m}, the output of wire 2 is approximated by
%\begin{equation}
%V_{2}(  t)\doteq V^1_2(  t-\Delta_1)+V^2_2(  t)+V^3_2(  t-\Delta_3),\label{eq:synch_3}
%\end{equation}
%where $V^i_2(t)$ is defined in Section~\ref{sec:5w}.
%We also have
%$V^2_2(  t)\doteq V^p_2-(V^p_2-V^f_2)\left(1-\frac{4}{3\pi}e^{-\frac{t}{\tau}}-\frac{8}{3\pi}e^{-\frac{t}{(1+3\lambda)\tau}}\right)$,
%$V^{i}_2(  t)\doteq \frac{4(V^p_{i}-V^f_{i})}{3\pi}\left(e^{-\frac{t}{\tau}}-e^{-\frac{t}{(1+3\lambda)\tau}}\right)$ for $i=1, 3$,
%where $\tau=\frac{8}{\pi^2}\tau_0$ and $V^p_i$ and $V^f_i$ denote the initial and final voltages of the transition on wire $i$, respectively.
%
%\begin{figure}[!tb]
%\begin{minipage}[b]{1.0\linewidth}
%\centering
%\centerline{\epsfig{figure=v2t,width=8.5cm}}
%\end{minipage}
%\caption{Waveforms of $V_2(t)$ and $V_2^i(t)$ for $i=1,2,3$.}
%\label{fig:v2t}
%\end{figure}
%
%We now approximate $t^{iC}_3$ based on Eq.~(\ref{eq:synch_3}). For the worst-case pattern $\uparrow \uparrow \uparrow$ in $0C$, the output of wire 2 is approximated by
%\begin{equation*}
%V_{2}(  t) \doteq  V^1_2(  t-\Delta_1)+V^2_2(t)+V^3_2(  t-\Delta_3).
%\end{equation*}
%When $\Delta_i = 0$ for $i=1,3$, the delay is given by $T_3^{0C}$, which is shown in Table~\ref{tab:1}. The waveforms of $V_2(t)$ and $V_2^i(t)$ for $i=1,2,3$ are shown in Fig.~\ref{fig:v2t}.
%At $t=T^{0C}_3$, $V^1_2(T^{0C}_3) = V^2_2(T^{0C}_3) = V^3_2(T^{0C}_3) \doteq \frac{1}{6}$. Solving $V^i_2(t) = \frac{1}{6}$ for $i=1,3$, we have another root $t\doteq T^{3C}_3$. When $T^{0C}_3 < t < T^{3C}_3$, $V^i_2(  t)>\frac{1}{6}$ for $i=1,3$. Depending on the time differences $\Delta_1$ and $\Delta_3$, we discuss the following cases:
%\begin{enumerate}
%\item If $T^{0C}_3 - T^{3C}_3 < \Delta_1, \Delta_3 < 0$, the two signals $V_2^1(t)$ and $V_2^3(t)$ are shifted to the left by at most $T^{3C}_3 - T^{0C}_3$. From Fig.~\ref{fig:v2t}, it is easy seen that $V^i_2(T^{0C}_3-\Delta_i)>\frac{1}{6}$ for $i=1,3$ and the delay $t^{0C}_3<T^{0C}_3$.
%\item If $\Delta_1<0<\Delta_3<T^{2C}_3$, we can get an upper bound of the delay by ignoring $V_2^1(t)$ and shifting $V_2^2(t)$ to the right to align with $V_2^3(t)$. We obtain the inequality $V_2(  t)>1-\frac{4}{3\pi} e^{-\frac{t-\Delta_3}{\tau}} -\frac{8}{3\pi} e^{-\frac{t-\Delta_3}{(1+3\lambda)\tau}} -\frac{4}{3\pi} e^{-\frac{t-\Delta_3}{\tau}} +\frac{4}{3\pi}e^{-\frac{t-\Delta_3}{(1+3\lambda)\tau}}$. Solving $V_2(  t)=0.5$, we have $t^{0C}_3<T^{1C}_3+\Delta_3$.
%\item If $0<\Delta_1<T^{2C}_3<\Delta_3$, we can get an upper bound of the delay by ignoring $V_2^3(t)$ and shifting $V_2^2(t)$ to the right to align with $V_2^1(t)$.
%We obtain the inequality $V_2(t)>1-\frac{4}{3\pi} e^{-\frac{t-\Delta_1}{\tau}} -\frac{8}{3\pi} e^{-\frac{t-\Delta_1}{(1+3\lambda)\tau}} -\frac{4}{3\pi} e^{-\frac{t-\Delta_1}{\tau}} +\frac{4}{3\pi}e^{-\frac{t-\Delta_1}{(1+3\lambda)\tau}}$. Then we have $t^{0C}_3<T^{1C}_3+\Delta_1$.
%\item If $0<\Delta_1<\Delta_3<T^{2C}_3$, we can get an upper bound of the delay by shifting $V_2^1(t)$ and $V_2^2(t)$ to the right to align with $V_2^3(t)$.
%We obtain the inequality $V_2(t)> -\frac{4}{3\pi} e^{-\frac{t-\Delta_3}{\tau}} +\frac{4}{3\pi} e^{-\frac{t-\Delta_3}{(1+3\lambda)\tau}}+ 1-\frac{4}{3\pi} e^{-\frac{t-\Delta_3}{\tau}} -\frac{8}{3\pi} e^{-\frac{t-\Delta_3}{(1+3\lambda)\tau}} -\frac{4}{3\pi} e^{-\frac{t-\Delta_3}{\tau}} +\frac{4}{3\pi}e^{-\frac{t-\Delta_3}{(1+3\lambda)\tau}}$. Then we have $t^{0C}_3<T^{0C}_3+\Delta_3$.
%\item In the following three cases, we can get an upper bound of the delay by ignoring $V_2^i(t)$ for $i=1,3$: (1) $\Delta_1<0$, $\Delta_3>T^{2C}_3$, (2) $\Delta_3>\Delta_1>T^{2C}_3$, (3) $\Delta_1<T^{0C}_3-T^{3C}_3, \;\Delta_3<0$. We obtain the inequality $V_2(t)> 1-\frac{4}{3\pi} e^{-\frac{t}{\tau}} -\frac{8}{3\pi} e^{-\frac{t}{(1+3\lambda)\tau}}$. Hence, we have $t^{0C}_3<T^{2C}_3$.
%\end{enumerate}
%
%
%%---commented out on Jan.12 2013
%%For the worst-case pattern $\uparrow \uparrow$- in $1C$, the output of wire $2$ is approximated by
%%\begin{equation*}
%%\begin{array}{lll} V_{2}(  t)&\doteq& V^1_2(  t-\Delta_1)+V^2_2(  t).
%%\end{array}
%%\end{equation*}
%%The delay is approximated using the same technique as for $\u\u\u$. At $t=T^{1C}_3$, $V^i_2(T^{1C}_3) \doteq  \frac{1}{4}$ for $i=1,2$. Solving $V^1_2(t) = \frac{1}{4}$, we have another root $t=T^{2C}_3$. Depending on the time difference $\Delta_1$, we discuss the following cases:
%%\begin{enumerate}
%%\item If $T^{1C}_3 - T^{2C}_3 < \Delta_1 < 0$, $V^1_2(T^{1C}_3-\Delta_1) > \frac{1}{4}$. Then we have $t^{1C}_3<T^{1C}_3$.
%%
%%\item If $0 < \Delta_1 < T^{2C}_3$, $V_2(t)=\frac{1}{2}>1-\frac{8}{3\pi} e^{-\frac{t-\Delta_1}{\tau}} -\frac{4}{3\pi} e^{-\frac{t-\Delta_1}{(1+3\lambda)\tau}}$. Then we have $t^{1C}_3<T^{1C}_3+\Delta_1$.
%%
%%\item If $\Delta_1 > T^{2C}_3$, or $\Delta_1 < T^{1C}_3 - T^{2C}_3$, we have $V_2(t)=\frac{1}{2}> 1-\frac{4}{3\pi} e^{-\frac{t}{\tau}} -\frac{8}{3\pi} e^{-\frac{t}{(1+3\lambda)\tau}}$. Then $t^{1C}_3 < T^{2C}_3$.
%%\end{enumerate}
%
%
%
%%Without loss of generality, we make the following assumptions. Since the $1C$ and $3C$ patterns have a transition on one of wires 1 and 3 and have no transition on the other, we consider patterns with transition on wire 1 only. Since the $0C$ and $4C$ patterns have the same transitions on wires 1 and 3, we assume $\Delta_1<\Delta_3$. For the $2C$ patterns $\downarrow \uparrow \uparrow$ and $\uparrow \uparrow \downarrow$, we consider the former. Under these assumptions, the approximate delays for all classes are given by (the assumptions are given in the parentheses).
%
%By a similar approach, we can obtain the worst delays of each class for a three-wire bus with synchronization problems, and they are summarized in Table~\ref{tab:sync3w}.
%For $0C$ and $4C$ classes, without loss of generality, we assume $\Delta_1<\Delta_3$, since the $0C$ and the $4C$ patterns have the same transitions on wires 1 and 3. For transition patterns with $\Delta_1>\Delta_3$, the result is obtained by switching $\Delta_1$ and $\Delta_3$. For $1C$ and $3C$ classes, we consider patterns with transitions on wire 1 only, since the $1C$ and the $3C$ patterns have a transition on one of wires 1 and 3 and have no transition on the other. For transition patterns with transitions on wire 3, the result is obtained by replacing $\Delta_1$ with $\Delta_3$. For $2C$ patterns, since $\downarrow \uparrow \uparrow$ and $\uparrow \uparrow \downarrow$ are symmetric to each other, we consider $\downarrow \uparrow \uparrow$ first. For $\uparrow \uparrow \downarrow$, the result is obtained by switching $\Delta_1$ and $\Delta_3$.
%
%\begin{table}[!thb]
%\caption{Revised three-wire model for synchronization issue.} \label{tab:sync3w}
%\begin{center}
%\begin{tabular}{|c|c|c|}
%\hline
%$t_3^{iC}$ & Delay & Condition \\
%\hline
%\hline
%& $T_3^{0C}$ & $T^{0C}_3-T^{3C}_3<\Delta_1<\Delta_3<0$ \\
%\cline{2-3}
%& $T^{1C}_3 +\Delta_3$ & $\Delta_1<0<\Delta_3<T^{2C}_3$ \\
%\cline{2-3}
%& $T^{1C}_3 +\Delta_1$ & $0<\Delta_1<T^{2C}_3<\Delta_3$ \\
%\cline{2-3}
%$t_3^{0C}$ & \multirow{3}{*}{$T^{2C}_3$} & $\Delta_1<0, \Delta_3>T^{2C}_3$ \\
%\cline{3-3}
%($\Delta_1 < \Delta_3$) & & $\Delta_3>\Delta_1>T^{2C}_3$ \\
%\cline{3-3}
%& & $\Delta_1<T^{0C}_3-T^{3C}_3, \Delta_3<0$ \\
%\cline{2-3}
%& $T^{0C}_3 + \Delta_3$ & $0<\Delta_1<\Delta_3<T^{2C}_3$ \\
%\hline
%\hline
%\multirow{4}{*}{$t_3^{1C}$} & $T^{1C}_3$ & $T^{1C}_3-T^{2C}_3<\Delta_1<0$ \\
%\cline{2-3}
%& $T^{1C}_3 +\Delta_1$ & $0<\Delta_1<T^{2C}_3$ \\
%\cline{2-3}
%& \multirow{2}{*}{$T^{2C}_3$} & $\Delta_1>T^{2C}_3$ \\
%\cline{3-3}
%& & $\Delta_1<T^{1C}_3-T^{2C}_3$ \\
%\hline
%\hline
%& \multirow{2}{*}{$T^{2C}_3$} & $\Delta_1<0,\Delta_3<T^{2C}_3-T^{1C}_3$ \\
%\cline{3-3}
%& & $\Delta_1>\left(\ln{\frac{16}{\pi}}\right)(1+3\lambda)\tau$ \\
%\cline{2-3}
%$t^{2C}_3$ & $T^{2C}_3+\Delta_3$ & $\Delta_1<0,\Delta_3>T^{2C}_3-T^{1C}_3$ \\
%\cline{2-3}
%($\Delta_1 < \Delta_3$) & $T^{3C}_3$ & $\Delta_1<0, \Delta_3>T^{3C}_3$ \\
%\cline{2-3}
%& $T^{3C}_3+\Delta_1$ & $0<\Delta_1<\left(\ln{\frac{16}{\pi}}\right)(1+3\lambda)\tau$ \\
%\hline
%
%& $T^{2C}_3$ & $\Delta_1>\left(\ln{\frac{16}{\pi}}\right)(1+3\lambda)\tau$ \\
%\cline{2-3}
%$t^{2C}_3$ & $T^{2C}_3+\Delta_1$ & $0<\Delta_3<\Delta_1<\left(\ln{\frac{16}{\pi}}\right)(1+3\lambda)\tau$ \\
%\cline{2-3}
%($\Delta_1 > \Delta_3$) & $T^{3C}_3$ & $\Delta_3<\Delta_1<0$ \\
%\cline{2-3}
%& $T^{3C}_3+\Delta_1$ & $\Delta_3<0,0<\Delta_1<\left(\ln{\frac{16}{\pi}}\right)(1+3\lambda)\tau$ \\
%\hline
%\hline
%\multirow{3}{*}{$t_3^{3C}$} & $T^{3C}_3$ & $\Delta_1<0$ \\
%\cline{2-3}
%& $T^{3C}_3 +\Delta_1$ & $0<\Delta_1<\left(\ln{\frac{16}{\pi}}\right)(1+3\lambda)\tau$ \\
%\cline{2-3}
%& $T^{2C}_3$ & $\Delta_1>\left(\ln{\frac{16}{\pi}}\right)(1+3\lambda)\tau$ \\
%\hline
%\hline
%& $T^{4C}_3$ & $\Delta_1<\Delta_3<0$ \\
%\cline{2-3}
%$t_3^{4C}$ & \multirow{2}{*}{$T^{4C}_3 +\Delta_3$} & $\Delta_1<0, \Delta_3>0$ \\
%\cline{3-3}
%($\Delta_1 < \Delta_3$) & & $\Delta_3>\Delta_1>0$ \\
%\hline
%\end{tabular}
%\end{center}
%\end{table}
%
%
%%\begin{enumerate}
%%\item $0C$ and $4C$ classes:
%%
%%Without loss of generality, we assume $\Delta_1<\Delta_3$, since the $0C$ and the $4C$ patterns have the same transitions on wires 1 and 3.
%%
%%
%%\begin{equation*}
%%t^{0C}_3=\left\{ \begin{array}{lll}
%%T^{0C}_3 & \mbox{if} & T^{0C}_3-T^{3C}_3<\Delta_1<\Delta_3<0,\\
%%&&\\
%%T^{1C}_3 +\Delta_3 & \mbox{if} & \Delta_1<0<\Delta_3<T^{2C}_3,\\
%%&&\\
%%T^{1C}_3 +\Delta_1 & \mbox{if} & 0<\Delta_1<T^{2C}_3<\Delta_3,\\
%%&&\\
%%T^{2C}_3 & \mbox{if} & \Delta_1<0, \Delta_3>T^{2C}_3,\\
%%T^{2C}_3 & \mbox{if} & \Delta_3>\Delta_1>T^{2C}_3,\\
%%T^{2C}_3 & \mbox{if} & \Delta_1<T^{0C}_3-T^{3C}_3, \Delta_3<0,\\
%%&&\\
%%T^{0C}_3 + \Delta_3 &\mbox{if} & 0<\Delta_1<\Delta_3<T^{2C}_3.\\
%%\end{array}
%%\right.
%%\end{equation*}
%%
%%\begin{equation*}
%%t^{4C}_3=\left \{ \begin{array}{lll}
%%T^{4C}_3 & \mbox{if} & \Delta_1<\Delta_3<0,\\
%%&&\\
%%T^{4C}_3+\Delta_3 & \mbox{if} & \Delta_1<0, \Delta_3>0,\\
%%T^{4C}_3+\Delta_3 & \mbox{if} & \Delta_3>\Delta_1>0.\\
%%\end{array} \right.
%%\end{equation*}
%%
%%
%%For transition patterns with $\Delta_1>\Delta_3$, the result is obtained by switching $\Delta_1$ and $\Delta_3$.\\
%%
%%\item $1C$ and $3C$ classes:
%%
%%Since the $1C$ and the $3C$ patterns have a transition on one of wires 1 and 3 and have no transition on the other, we consider patterns with transitions on wire 1 only. We have
%%
%%\begin{equation*}
%%t^{1C}_3=\left \{ \begin{array}{lll}
%%T^{1C}_3 & \mbox{if} & T^{1C}_3-T^{2C}_3<\Delta_1<0,\\
%%&&\\
%%T^{1C}_3+\Delta_1 & \mbox{if} & 0<\Delta_1<T^{2C}_3,\\
%%&&\\
%%T^{2C}_3 & \mbox{if} & \Delta_1>T^{2C}_3,\\
%%T^{2C}_3 & \mbox{if} & \Delta_1<T^{1C}_3-T^{2C}_3.\\
%%\end{array} \right.
%%\end{equation*}
%%
%%\begin{equation*}
%%t^{3C}_3=\left \{ \begin{array}{lll}
%%T^{3C}_3 & \mbox{if} & \Delta_1<0,\\
%%&&\\
%%T^{3C}_3+\Delta_1 & \mbox{if} & 0<\Delta_1<\left(\ln{\frac{16}{\pi}}\right)\tau_1,\\
%%&&\\
%%T^{2C}_3 & \mbox{if} & \Delta_1>\left(\ln{\frac{16}{\pi}}\right)\tau_1.\\
%%\end{array} \right.
%%\end{equation*}
%%
%%For transition patterns with transitions on wire 3, the result is obtained by replacing $\Delta_1$ with $\Delta_3$.\\
%%
%%\item $2C$ class:
%%
%%Since the $2C$ patterns $\downarrow \uparrow \uparrow$ and $\uparrow \uparrow \downarrow$ are symmetric to each other, we consider $\downarrow \uparrow \uparrow$ first. Assume $\Delta_1<\Delta_3$, we have
%%
%%\begin{equation*}
%%t^{2C}_3=\left \{ \begin{array}{lll}
%%T^{2C}_3 & \mbox{if} & \Delta_1<0,\Delta_3<T^{2C}_3-T^{1C}_3,\\
%%T^{2C}_3 & \mbox{if} & \Delta_1>\left(\ln{\frac{16}{\pi}}\right)\tau_1,\\
%%&&\\
%%T^{2C}_3+\Delta_3 & \mbox{if} & \Delta_1<0,\Delta_3>T^{2C}_3-T^{1C}_3,\\
%%&&\\
%%T^{3C}_3 & \mbox{if} & \Delta_1<0, \Delta_3>T^{3C}_3,\\
%%&&\\
%%T^{3C}_3+\Delta_1 & \mbox{if} & 0<\Delta_1<\left(\ln{\frac{16}{\pi}}\right)\tau_1.\\
%%\end{array} \right.
%%\end{equation*}
%%
%%Assume $\Delta_1>\Delta_3$, we have
%%
%%\begin{equation*}
%%t^{2C}_3=\left \{ \begin{array}{lll}
%%T^{2C}_3 & \mbox{if} & \Delta_1>\left(\ln{\frac{16}{\pi}}\right)\tau_1,\\
%%&&\\
%%T^{2C}_3+\Delta_1 & \mbox{if} & 0<\Delta_3<\Delta_1<\left(\ln{\frac{16}{\pi}}\right)\tau_1,\\
%%&&\\
%%T^{3C}_3 & \mbox{if} & \Delta_3<\Delta_1<0,\\
%%&&\\
%%T^{3C}_3+\Delta_1 & \mbox{if} & \Delta_3<0,0<\Delta_1<\left(\ln{\frac{16}{\pi}}\right)\tau_1.\\
%%\end{array} \right.
%%\end{equation*}
%%
%%For $\uparrow \uparrow \downarrow$, the result is obtained by switching $\Delta_1$ and $\Delta_3$.
%%\end{enumerate}
%
%
%
%
%\subsection{Five-wire model with synchronization problems}
%\label{sec:sync5}
%We now focus on wire 3 of a five-wire bus, and approximate $t^{iC}_5$ based on $\Delta_2$ and $\Delta_4$. The output of wire 3 in the worst case is approximated by
%\begin{equation*}
%V_{3}(  t) \doteq  V^2_3(  t-\Delta_2)+V^3_3(  t)+V^4_3(  t-\Delta_4),
%\end{equation*}
%where
%$V^3_3(  t) \doteq V^p_3-(V^p_3-V^f_3) \left(1+\frac{4}{3\pi}e^{-\frac{t}{\tau}}-\frac{16}{3\pi}e^{-\frac{t}{(1+\frac{3}{2}\lambda)\tau}}\right)$ and
%$V^{i}_3(t) \doteq \frac{4(V^p_{i}-V^f_{i})}{3\pi}\left( e^{-\frac{t}{\tau}}-e^{-\frac{t}{(1+3\lambda)\tau}}\right)$ for $i=2, 4$.
%
%For the worst-case pattern $\downarrow \uparrow \uparrow \uparrow \downarrow$ in $0C$, the output of wire 3 is approximated by
%\begin{equation*}
%V_{3}(t)\doteq V^2_3(t-\Delta_2)+V^3_3(t)+V^4_3(t-\Delta_4),
%\end{equation*}
%where $V^3_3(  t) \doteq 1+\frac{4}{3\pi}e^{-\frac{t}{\tau}}-\frac{16}{3\pi}e^{-\frac{t}{(1+\frac{3}{2}\lambda)\tau}}$, $V^{i}_3(  t) \doteq \frac{4}{3\pi}\left(e^{-\frac{t}{(1+3\lambda)\tau}} - e^{-\frac{t}{\tau}}\right)$,
%and $\tau=\frac{8}{\pi^2}\tau_0$. At $t=T^{0C}_5$, $V^2_3(T^{0C}_5) = V^4_3(T^{0C}_5) \doteq  0.360$, $V^3_3(T^{0C}_5) \doteq -0.220$.
%Solving $V^i_3(t) = 0.360$ for $i=2, 4$, we have another root $t=1.89\tau$.
%For $ 1.89\tau < t < T^{0C}_5$, $V^i_3(t)>0.360$ for $i=2, 4$.  Depending on the time differences $\Delta_2$ and $\Delta_4$, we discuss the following cases:
%\begin{enumerate}
%\item If $0 < \Delta_2< \Delta_4 < T^{0C}_5 -1.89\tau$,
%$V^i_3(T^{0C}_5-\Delta_i)>0.360$ for $i=2, 4$. Then we have
%$t^{0C}_5<T^{0C}_5$.
%\item If $T^{0C}_5 -1.89\tau < \Delta_2< \Delta_4 $,
%$V_{3}(t)< V^2_3(t-\Delta_4)+V^3_3(t-\Delta_4)+V^4_3(t-\Delta_4).$ Then we have
%$t^{0C}_5<T^{0C}_5+\Delta_4$.
%
%\item If $\Delta_2< 0 < \Delta_4$, $V_{3}(t)< V^3_3(t-\Delta_4)+V^4_3(t-\Delta_4).$ Then we have $t^{0C}_5<T^{1C}_5+\Delta_4$.
%
%\item If $\Delta_2 < \Delta_4 < 0$, $V_{3}(t)< V^3_3(t).$ Then we have $t^{0C}_5<T^{2C}_5$.
%\end{enumerate}
%
%
%%For the worst-case pattern $\downarrow \uparrow \uparrow$-$\downarrow$ in $1C$, the output of wire $3$ is approximated by
%%\begin{equation*}
%%V_{3}(t) \doteq V^2_3(t-\Delta_2)+V^3_3(t).
%%\end{equation*}
%%At $t=T^{1C}_5$, $V^2_3(T^{1C}_5) \doteq  0.289$, $V^3_3(T^{1C}_5) \doteq 0.211$.
%%Solving $V^2_3(t) = 0.289$, we have $t=2.27\tau$.
%%For $ 2.27\tau < t < T^{1C}_5$, $V^2_3(t)>0.289$.
%%Depending on the time differences $\Delta_2$ and $\Delta_4$, we discuss the following cases:
%%\begin{enumerate}
%%\item If $ 0< \Delta_2< T^{1C}_5 -2.27\tau$, $V^i_3(T^{1C}_5-\Delta_2)>0.289$. Then we have
%%$t^{1C}_5<T^{1C}_5$.
%%
%%\item If $ \Delta_2 > T^{1C}_5 -2.27\tau $, $V_{3}(t)> V^2_3(t-\Delta_2) + V^3_3(t-\Delta_2).$ Then we have
%%$t^{1C}_5<T^{1C}_5+ \Delta_2$.
%%
%%\item If $ \Delta_2 < 0 $, $V_{3}(t)> V^3_3(t).$ Then we have $t^{1C}_5<T^{2C}_5$.
%%\end{enumerate}
%
%
%%By a similar approach, we can obtain the worst delays of each class for a five-wire bus with synchronization problems, and they are summarized below.
%
%By a similar approach, we can obtain the worst delays of each class for a five-wire bus with synchronization problems, and they are summarized in Table~\ref{tab:sync5w}.
%For $0C$ and $4C$ classes, without loss of generality, we assume $\Delta_2<\Delta_4$, since the $0C$ and the $4C$ patterns have the same transitions on wires 2 and 4. For transition patterns with $\Delta_2>\Delta_4$, the result is obtained by switching $\Delta_2$ and $\Delta_4$. For $1C$ and $3C$ classes, we consider patterns with transitions on wire 2 only, since the $1C$ and the $3C$ patterns have a transition on one of wires 2 and 4 and have no transition on the other. For transition patterns with transitions on wire 4, the result is obtained by replacing $\Delta_2$ with $\Delta_4$. For $2C$ patterns, since $\downarrow \downarrow \uparrow \uparrow \downarrow$ and $\downarrow \uparrow \uparrow \downarrow \downarrow$ are symmetric to each other, we consider $\downarrow \downarrow \uparrow \uparrow \downarrow$ first. For $\downarrow \uparrow \uparrow \downarrow \downarrow$, the result is obtained by switching $\Delta_2$ and $\Delta_4$.
%
%
%\begin{table}[!thb]
%\caption{Revised five-wire model for synchronization issue, where $K_0=T^{0C}_5-1.89\tau$, $K_1=T^{1C}_5-2.27\tau$, $K_2=T^{3C}-0.94\tau$, $K_3=T^{2C}_5-1.42\tau$, and $K_4=2.32\left(1+\frac{3}{2}\lambda\right)\tau$.} \label{tab:sync5w}
%\begin{center}
%\begin{tabular}{|c|c|c|}
%\hline
%$t_5^{iC}$ & Delay & Condition \\
%\hline
%\hline
%& $T_5^{0C}$ & $0<\Delta_2<\Delta_4<K_0$ \\
%\cline{2-3}
%$t_5^{0C}$ & $T^{0C}_5 +\Delta_4$ & $K_0 <\Delta_2 < \Delta_4$ \\
%\cline{2-3}
%($\Delta_2 < \Delta_4$) & $T^{1C}_5 +\Delta_4$ & $\Delta_2<0<\Delta_4$ \\
%\cline{2-3}
%& $T^{2C}_5$ & $\Delta_2<\Delta_4<0$ \\
%\hline
%\hline
%\multirow{3}{*}{$t_5^{1C}$} & $T^{1C}_5$ & $0<\Delta_2<K_1$ \\
%\cline{2-3}
%& $T^{1C}_5+\Delta_2$ & $\Delta_2>K_1$ \\
%\cline{2-3}
%& $T^{2C}_5$ & $\Delta_2<0$ \\
%\hline
%\hline
%& \multirow{2}{*}{$T^{2C}_5$} & $\Delta_2<0,\Delta_4<K_3$ \\
%\cline{3-3}
%& & $\Delta_2>K_4$ \\
%\cline{2-3}
%$t^{2C}_5$ & $T^{2C}_5+\Delta_4$ & $\Delta_2<0,\Delta_4>K_3$ \\
%\cline{2-3}
%($\Delta_2 < \Delta_4$) & $T^{3C}_5$ & $\Delta_2<0, \Delta_4>T^{3C}_5$ \\
%\cline{2-3}
%& $T^{3C}_5+\Delta_2$ & $0<\Delta_2<K_4$ \\
%\hline
%
%& $T^{2C}_5$ & $\Delta_2>K_4$ \\
%\cline{2-3}
%$t^{2C}_5$ & $T^{2C}_5+\Delta_2$ & $0<\Delta_4<\Delta_2<K_4$ \\
%\cline{2-3}
%($\Delta_2 > \Delta_4$) & $T^{3C}_5$ & $\Delta_4<\Delta_2<0$ \\
%\cline{2-3}
%& $T^{3C}_5+\Delta_2$ & $\Delta_4<0<\Delta_2<K_4$ \\
%\hline
%\hline
%\multirow{3}{*}{$t_5^{3C}$} & $T^{3C}_5$ & $\Delta_2<0$ \\
%\cline{2-3}
%& $T^{3C}_5+\Delta_2$ & $0<\Delta_2<K_2$ \\
%\cline{2-3}
%& $T^{2C}_5$ & $\Delta_2>K_2$ \\
%\hline
%\hline
%& $T^{4C}_5$ & $\Delta_2<\Delta_4<0$ \\
%\cline{2-3}
%$t_5^{4C}$ & \multirow{2}{*}{$T^{4C}_5+\Delta_4$} & $\Delta_2<0, \Delta_4>0$ \\
%\cline{3-3}
%($\Delta_2 < \Delta_4$) & & $\Delta_4>\Delta_2>0$ \\
%\hline
%\end{tabular}
%\end{center}
%\end{table}
%
%
%%\begin{enumerate}
%%\item $0C$ and $4C$ classes:
%%
%%Without loss of generality, we make the same assumptions as before. For the $0C$ and $4C$ patterns, we assume $\Delta_2<\Delta_4$.
%%
%%
%%
%%
%%\begin{equation*}
%%t^{0C}_5=\left\{ \begin{array}{lll}
%%T^{0C}_5 & \mbox{if} & 0<\Delta_2<\Delta_4<K_0,\\
%%&&\\
%%T^{0C}_5 +\Delta_4 & \mbox{if} & K_0 <\Delta_2 < \Delta_4\\
%%&&\\
%%T^{1C}_5 +\Delta_4 & \mbox{if} & \Delta_2<0<\Delta_4,\\
%%&&\\
%%T^{2C}_5 & \mbox{if} & \Delta_2<\Delta_4<0,\\
%%\end{array}
%%\right.
%%\end{equation*}
%%where $K_0=T^{0C}_5-1.89\tau$.
%%
%%\begin{equation*}
%%t^{4C}_5=\left \{ \begin{array}{lll}
%%T^{4C}_5 & \mbox{if} & \Delta_2<\Delta_4<0,\\
%%&&\\
%%T^{4C}_5+\Delta_4 & \mbox{if} & \Delta_2<0, \Delta_4>0,\\
%%T^{4C}_5+\Delta_4 & \mbox{if} & \Delta_4>\Delta_2>0.\\
%%\end{array} \right.
%%\end{equation*}
%%
%%
%%For patterns with $\Delta_2>\Delta_4$, the result is obtained by switching $\Delta_2$ and $\Delta_4$.\\
%%
%%\item $1C$ and $3C$ classes:
%%
%%Since the $1C$ and $3C$ patterns have a transition on one of wires 2 and 4 and have no transition on the other wire, we consider patterns with a transition on wire 2 only. We have
%%
%%
%%
%%\begin{equation*}
%%t^{1C}_5=\left \{ \begin{array}{lll}
%%T^{1C}_5 & \mbox{if} & 0<\Delta_2<K_1,\\
%%&&\\
%%T^{1C}_5+\Delta_2 & \mbox{if} & \Delta_2>K_1,\\
%%&&\\
%%T^{2C}_5 & \mbox{if} & \Delta_2<0,\\
%%\end{array} \right.
%%\end{equation*}
%%where $K_1=T^{1C}_5-2.27\tau$.
%%
%%\begin{equation*}
%%t^{3C}_5=\left \{ \begin{array}{lll}
%%T^{3C}_5 & \mbox{if} & \Delta_2<0,\\
%%&&\\
%%T^{3C}_5+\Delta_2 & \mbox{if} & 0<\Delta_2<K_2,\\
%%&&\\
%%T^{2C}_5 & \mbox{if} & \Delta_2>K_2.\\
%%\end{array} \right.
%%\end{equation*}
%%where $K_2=1.63(1+\frac{3}{2}\lambda)\tau$.
%%
%%For patterns with a transition on wire 4, the result is obtained by replacing $\Delta_2$ with $\Delta_4$.\\
%%
%%\item $2C$ class:
%%
%%For the $2C$ patterns $\downarrow \downarrow \uparrow \uparrow \downarrow$ and $\downarrow \uparrow \uparrow \downarrow \downarrow$, they are symmetric to each other. We consider $\downarrow \downarrow \uparrow \uparrow \downarrow$ first.
%%Assume $\Delta_2<\Delta_4$, we have
%%
%%
%%
%%\begin{equation*}
%%t^{2C}_5=\left \{ \begin{array}{lll}
%%T^{2C}_5 & \mbox{if} & \Delta_2<0,\Delta_4<K_3,\\
%%T^{2C}_5 & \mbox{if} & \Delta_2>K_4,\\
%%&&\\
%%T^{2C}_5+\Delta_4 & \mbox{if} & \Delta_2<0,\Delta_4>K_3,\\
%%&&\\
%%T^{3C}_5 & \mbox{if} & \Delta_2<0, \Delta_4>T^{3C}_5,\\
%%&&\\
%%T^{3C}_5+\Delta_2 & \mbox{if} & 0<\Delta_2<K_4.\\
%%\end{array} \right.
%%\end{equation*}
%%
%%Assume $\Delta_2>\Delta_4$, we have
%%\begin{equation*}
%%t^{2C}_5=\left \{ \begin{array}{lll}
%%T^{2C}_5 & \mbox{if} & \Delta_2>K_4,\\
%%&&\\
%%T^{2C}_5+\Delta_2 & \mbox{if} & 0<\Delta_4<\Delta_2<K_4,\\
%%&&\\
%%T^{3C}_5 & \mbox{if} & \Delta_4<\Delta_2<0,\\
%%&&\\
%%T^{3C}_5+\Delta_2 & \mbox{if} & \Delta_4<0<\Delta_2<K_4,\\
%%\end{array} \right.
%%\end{equation*}
%%where $K_3=T^{2C}_5-1.42\tau$, $K_4=2.32\left(1+\frac{3}{2}\lambda\right)\tau$.
%%
%%For $\downarrow \uparrow \uparrow \downarrow \downarrow$, the result is obtained by switching $\Delta_2$ and $\Delta_4$.
%%\end{enumerate}
%
%\begin{table}[h]
%\caption{Simulated results of a three-wire bus with synchronization problems ($T^{iC}_3$=1.08, 1.87, 22.98, 40.59, 53.08, respectively). All the delays are in $\mathrm{ps}$.}\label{tab:7}
%\begin{center}
%\begin{tabular}{|r|c|c|c|c|}
%\hline
%$iC$ & $\Delta_1$ & $\Delta_3$ & Sim.  & $t^{ic}_3$ \\
%\hline
%\multirow{7}{*}{$0C$} & -20 & -30 & 0 & 1.08\\
%\cline{2-5}
% & -100 & 10 & 10.70 & 11.87\\
%\cline{2-5}
% & 10 & 30 & 10.89 & 11.87\\
%\cline{2-5}
%& -200 & 30 & 22.67 & 22.98\\
%\cline{2-5}
%& 50 & 100 & 22.91 & 22.98\\
%\cline{2-5}
%& -100 & -50 & 20.46 & 22.98\\
%\cline{2-5}
%& 10 & 20 & 10.89 & 21.08\\
%\hline
%
%\multirow{4}{*}{$1C$}& -10 & - & 1.27 & 1.87\\
%\cline{2-5}
%& 20 &  - & 20.13 & 21.87\\
%\cline{2-5}
%& 40 & - & 20.91 & 22.98\\
%\cline{2-5}
%& -40 & - & 10.65 & 22.98\\
%\hline
%
%\multirow{9}{*}{$2C$}& -50 & 10 & 11.69 & 22.98\\
%\cline{2-5}
%& 100 & 150 & 22.91 & 22.98\\
%\cline{2-5}
%& -50 & 30 & 29.55 & 52.98\\
%\cline{2-5}
%& -50 & 50 & 29.56 & 40.59\\
%\cline{2-5}
%& 50 & 100 & 63.72 & 90.89\\
%\cline{2-5}
%& 100 & 50 & 22.91 & 22.98\\
%\cline{2-5}
%& 20 & 10 & 27.27 & 42.98\\
%\cline{2-5}
%& -50 & -100 & 27.56 & 40.59\\
%\cline{2-5}
%& 50 & -200 & 63.62 & 90.59\\
%\hline
%
%\multirow{3}{*}{$3C$}& -100 &  - & 25.17 & 40.59\\
%\cline{2-5}
%& 50 & - & 63.72 & 90.59\\
%\cline{2-5}
%& 100 & - & 22.91 & 22.98\\
%\hline
%
%\multirow{3}{*}{$4C$}& -200 & -100 & 25.39 & 53.08\\
%\cline{2-5}
%& -100 & 50 & 64.72 & 103.08\\
%\cline{2-5}
%& 50 & 100 & 109.57 & 153.08\\
%\hline
%\end{tabular}
%\end{center}
%\end{table}
%
%
%\begin{table}[h]
%\caption{Simulated results of a five-wire bus with synchronization problems ($T^{iC}_5$=7.16, 13.46, 27.24, 40.59, 53.08, respectively). All the delays are in $\mathrm{ps}$.}\label{tab:8}
%\begin{center}
%\begin{tabular}{|r|c|c|c|c|}
%\hline
%$iC$ & $\Delta_2$ & $\Delta_4$ & Sim.  & $t^{ic}_5$ \\
%\hline
%\multirow{7}{*}{$0C$} & 2 & 4 & 10.69 & 7.16\\
%\cline{2-5}
%& 10 & 15 & 15.70 & 22.16\\
%\cline{2-5}
%& -100 & 20 & 20.87 & 28.46\\
%\cline{2-5}
%& -200 & -100 & 23.93 & 27.24\\
%\hline
%
%\multirow{4}{*}{$1C$}& 5 & - & 17.11 & 13.46\\
%\cline{2-5}
%& 20 &  - & 21.22 & 33.46\\
%\cline{2-5}
%& -100 & - & 24.20 & 27.24\\
%\hline
%
%\multirow{9}{*}{$2C$}& -50 & 20 & 22.62 & 27.24\\
%\cline{2-5}
%& 100 & 150 & 26.01 & 27.24\\
%\cline{2-5}
%& -50 & 30 & 29.99 & 57.24\\
%\cline{2-5}
%& -50 & 50 & 30.62 & 40.59\\
%\cline{2-5}
%& 20 & 50 & 40.23 & 60.59\\
%\cline{2-5}
%& 60 & 20 & 21.22 & 27.24\\
%\cline{2-5}
%& 40 & 10 & 17.44 & 37.24\\
%\cline{2-5}
%& -50 & -100 & 28.76 & 40.59\\
%\cline{2-5}
%& 10 & -100 & 36.55 & 50.59\\
%\hline
%
%\multirow{3}{*}{$3C$}& -20 &  - & 34.73 & 40.59\\
%\cline{2-5}
%& 20 & - & 47.85 & 60.59\\
%\cline{2-5}
%& 50 & - & 2.35 & 27.24\\
%\hline
%
%\multirow{3}{*}{$4C$}& -100 & -50 & 31.53 & 53.08\\
%\cline{2-5}
%& -50 & 50 & 63.88 & 103.08\\
%\cline{2-5}
%& 30 & 50 & 81.66 & 103.08\\
%\hline
%\end{tabular}
%\end{center}
%\end{table}
%
%
%%\begin{table}[h]
%%\caption{Simulated results of a five-wire bus with synchronization problems ($\tau_{dist}=3.75\mathrm{ps}$, $\lambda=10$, $T^{iC}_5$=19.18, 34.99, 59.46, 88.08, 115.18, respectively). All the delays are in $\mathrm{ps}$.}\label{tab:8}
%%\begin{center}
%%\begin{tabular}{|r|c|c|c|c|c|c|c|c|c|}
%%\hline
%%$iC$ & $\Delta_2$ & $\Delta_4$ & Sim.  & $t^{ic}_5$ & $iC$ & $\Delta_2$ & $\Delta_4$ & Sim.  & $t^{ic}_5$\\
%%\hline
%%\multirow{7}{*}{$0C$} & 5 & 8 & 24.07 & 19.18 & \multirow{2}{*}{$2C$} & 50 & 100 & 88.20 & 138.08\\
%%\cline{2-5}
%%\cline{7-10}
%% & 15 & 20 & 27.05 & 39.18 & & 200 & 100 & 56.53 & 59.46\\
%%\cline{2-5}
%%\cline{6-10}
%%& -100 & 20 & 30.70 & 54.99 & & 100 & 50 & 51.60 & 159.46\\
%%\cline{2-5}
%%\cline{7-10}
%%& -200 & -100 & 42.03 & 59.46 & & -50 & -200 & 67.99 & 88.08\\
%%\cline{1-5}
%%\cline{7-10}
%%
%%\multirow{4}{*}{$1C$}& 20 & - & 37.82 & 34.99 & & 50 & -200 & 82.20 & 138.08\\
%%\cline{2-5}
%%\cline{6-10}
%%& 40 &  - & 44.13 & 74.99 & \multirow{3}{*}{$3C$}& -100 &  - & 65.35 & 88.08\\
%%\cline{2-5}
%%\cline{7-10}
%%& -100 & - & 46.35 & 59.46 & & 100 & - & 133.47 & 188.08\\
%%\cline{2-5}
%%& 100 & - & 56.58 & 59.46 & & 200 & - & 49.71 & 59.46\\
%%\cline{1-5}
%%\cline{6-10}
%%
%%\multirow{2}{*}{$2C$}& -50 & 20 & 49.81 & 59.46 & \multirow{3}{*}{$4C$}& -200 & -100 & 70.07 & 115.18\\
%%\cline{2-5}
%%\cline{7-10}
%%& 120 & 200 & 56.58 & 59.46 & & -100 & 100 & 140.62 & 215.18\\
%%\cline{2-5}
%%\cline{7-10}
%%& -50 & 60 & 62.52 & 119.46 & & 50 & 100 & 162.82 & 215.18\\
%%\cline{2-5}
%%& -50 & 100 & 72.75 & 88.08 & & & & &\\
%%\hline
%%\end{tabular}
%%\end{center}
%%\end{table}
%
%\subsection{Performance evaluation}
%Based on our three-wire and five-wire models, we observe \textbf{two possible scenarios} with regard to the impact of synchronization problems on the delay. When the time differences are relatively small, the delay is increased only by the time differences. When the time differences are sufficiently large, they can change the worst delay of a class to a different class. For instance, the delays of the transition patterns in $0C$ and $1C$ may be increased to those of $2C$ when the time differences are large enough, and similarly $2C$ to $3C$. This is consistent with the observation in \cite{Dua04}. On the other hand, the delays of the transition patterns in $3C$ may decrease to those of $2C$ class when the time differences are large enough. Intuitively, this is because large time differences change the intended transition patterns into different patterns.
%
%
%%
%%For the CAC design on a bus with synchronization problems, the skew can affect the overall delay. If the codebook has already been chosen (for example, the worst allowable patterns are $2C$ patterns), and the maximum allowable delay given, there is a constraint on the value of the skew. The skew in return gives requirements on the circuit design where skew might originate.
%
%To evaluate the performance of our model, we simulate the three- and five-wire buses in the presence of synchronization problems. In our simulation, we assume that the clock period $T$ is 1ns, and that the maximum allowable skew is 500 ps. Our assumptions appear reasonable for high-speed repeaters, for which the skew between different outputs can be as large as 500 ps and the clock period $T$ is greater than 1ns~\cite{Giga}.
%
%For a three-wire bus with synchronization problems, the comparison of simulated delays for each transition class and delays produced by our model is shown in Table~\ref{tab:7}. The rows in Table~\ref{tab:7} correspond to all the cases of $t^{iC}_3$ in Section~\ref{sec:sync3}, appearing in the same order.
%For a five-wire bus with synchronization problems, the comparison of simulated delays for each transition class and delays produced by our model is shown in Table~\ref{tab:8}. The rows in Table~\ref{tab:8} correspond to all the cases of $t^{iC}_5$ in Section~\ref{sec:sync5}, appearing in the same order.
%
%As Tables~\ref{tab:7} and \ref{tab:8} show, the delays given by our modified three-wire and five-wire models either bound from above or closely approximate the simulated delays for all transition patterns. The results in Tables~\ref{tab:7} and \ref{tab:8} also verify the above observations about two possible scenarios.
%
%%Our results have significant ramification on the design of CACs. For instance, we observe that when the synchronization problems are sufficient severe, the actual delays for CACs that target small delays are much larger. CACs achieve a smaller target delay at the expense of a lower rate, that is, they need more extra wires to protect the same number of data wires. Depending on the severity of the synchronization problems, our results can be used to select the appropriate CACs.
%
%
%\subsection{Impact on CACs}
%Our delay models above can help to evaluate the effectiveness of CACs as well as to design CACs for a bus with synchronization problems. Given a CAC and the worst possible skew, our models either bound or closely approximate the delay of the bus.
%
%Our delay models also have significant ramification on the design of CACs. First, our delay models directly impact the selection of existing CACs in the presence of synchronization problems by  clearly quantifying the impact of synchronization problems on the worst delays of CACs. As observed above, depending on the severity of the synchronization problems, the effectiveness of CACs is affected to a varying extent. Furthermore, the sensitiveness to time differences varies with CACs. Hence, our delay models help designers to select the appropriate CACs based on expected time differences.
%%For instance, when the time differences between wires are relatively small, the worst delays of CACs are increased slightly. However, when the time differences are over certain thresholds, the actual worst delays of CACs become significantly greater.
%More importantly, our delay models lead to more efficient CACs. Our delay models presented in this paper have used the same classification of transition patterns as the model in \cite{Sot01}. In a separate work \cite{SWY_sips11_CAC,SWY_J11_CAC}, using our delay models we propose a different classification of transition patterns and more efficient CACs.


\section{Conclusions and future work}\label{sec:conclusion}
In this paper, we propose improved analytical delay models for coupled interconnects. We first derive closed-form expressions of the signals on the bus, based on the distributed RC model, and then approximate the delays of different patterns by evaluating these closed-form expressions. We focus on three-wire and five-wire models, and simulation results show that our model has better accuracy than the model in \cite{Sot01}. Although our models are based on three-wire and five-wire buses, they are not limited to these two cases. For a bus with more than five wires, our five-wire model can still approximate delays better than the model in \cite{Sot01}. 
%To account for different switching instants of wires, we also refine our delay models, and evaluate the impact of synchronization problems on bus delays. To our best knowledge, this is the first analytical work for this problem. 
%Simulation results show that our refined models either bound from above or closely approximate delays for all transition patterns in the presence of synchronization problems. For some classes, the upper bounds by our models are not tight in the presence of synchronization problems; we plan to address this problem in our future work.

%\appendix
%\subsection{Revised models with consideration of the buffer effect}
%In the previous derivation, the buffer effect is ignored with assumption that the driver resistance and loading capacitance are relatively small. However, the choice of buffers may impact the results significantly, if the driver resistance and loading capacitance are relatively large. To capture the buffer effect, we revise our models with incorporation of $R_S$ and $C_L$.
%
%First, we focus on our three-wire model. With consideration of buffer effect, the differential equation is still give by Eq.~(\ref{Eq:2}). Only the boundary conditions need to be changed. The revised boundary conditions are given by
%\begin{equation*}
%\left\{\begin{array}{l}
%V_i(0,t) = V_i^p-(V_i^p-V_i^f) u(t)-I_i(0,t) R_S \\
%I_i(L,t)=C_L \frac{\partial}{\partial t}V_i(L,t)
%\end{array} \mbox{ for } i=1,2,3 \right.
%\end{equation*}
%
%
%By solving the differential equations of a three-wire bus, the expressions of all class patterns are given in Tab. \ref{tab:3dif}, where $K^3_1 = -1.01 \frac{R_T+C_T+1}{R_T+C_T+\frac{\pi}{4}}$, $K^3_2 = -1.01 \frac{R_T+C_T^\ast+1}{R_T+C_T^\ast+\frac{\pi}{4}}$, $\tau_1 = \frac{RC(R_TC_T+R_T+C_T+(\frac{2}{\pi})^2)}{1.04}$,  $\tau_2 = \frac{(1+3\lambda) RC(R_TC_T^\ast+R_T+C_T^\ast+(\frac{2}{\pi})^2)}{1.04}$,  $R_T=\frac{R_S}{rL}$, $C_T=\frac{C_L}{cL}$, $C_T^\ast=\frac{C_L}{(1+3\lambda)cL}$, $C=cL$, and $R=rL$.
%
%\begin{table}
%\caption{Expressions of middle wire in a three-wire model.} \label{tab:3dif}
%\begin{center}
%\begin{tabular}{|c|c|c|}
%\hline
%$iC$ & $V_2(L,t)$ & Delay\\
%\hline
%$0C$ & $1-K^3_1 e^{-\frac{t}{\tau_1}}$ & $(\ln 2K^3_1)\tau_1$\\
%\hline
%$1C$ & $1-\frac{2}{3}K^3_1 e^{-\frac{t}{\tau_1}}-\frac{1}{3}K^3_2 e^{-\frac{t}{\tau_2}}$ & $(\ln \frac{4K^3_1}{3})\tau_1$\\
%\hline
%$2C$ & $1-\frac{1}{3}K^3_1 e^{-\frac{t}{\tau_1}}-\frac{2}{3}K^3_2 e^{-\frac{t}{\tau_2}}$ & $(\ln \frac{4K^3_2}{3})\tau_2$\\
%\hline
%$3C$ & $1-K^3_2 e^{-\frac{t}{\tau_2}}$ & $(\ln 2K^3_2)\tau_2$\\
%\hline
%$4C$ & $1+\frac{1}{3}K^3_1 e^{-\frac{t}{\tau_1}}-\frac{4}{3}K^3_2 e^{-\frac{t}{\tau_2}}$ & $(\ln \frac{8K^3_2}{3})\tau_2$\\
%\hline
%\end{tabular}
%\end{center}
%\end{table}
%
%Similarly, for a five-wire bus, the expressions of worst-case patterns in each class can be derived shown in Tab. \ref{tab:5dif}, where $K^5_1 = -1.01 \frac{R_T+C_T+1}{R_T+C_T+\frac{\pi}{4}}$, $K^5_2 = -1.01 \frac{R_T+C_T^\ast+1}{R_T+C_T^\ast+\frac{\pi}{4}}$, $K^5_3 = -1.01 \frac{R_T+C_T^\dagger+1}{R_T+C_T^\dagger+\frac{\pi}{4}}$, $\tau_1 = \frac{RC(R_TC_T+R_T+C_T+(\frac{2}{\pi})^2)}{1.04}$,  $\tau_2 = \frac{(1+\frac{3}{2}\lambda) RC(R_TC_T^\ast+R_T+C_T^\ast+(\frac{2}{\pi})^2)}{1.04}$, $\tau_3 = \frac{(1+3\lambda) RC(R_TC_T^\dagger+R_T+C_T^\dagger+(\frac{2}{\pi})^2)}{1.04}$,  $R_T=\frac{R_S}{rL}$, $C_T=\frac{C_L}{cL}$, $C_T^\ast=\frac{C_L}{(1+\frac{3\lambda}{2})cL}$, $C_T^\dagger=\frac{C_L}{(1+3\lambda)cL}$, $C=cL$, and $R=rL$.
%
%All the delays can be approximated as closed-form expressions, except for $0C$ and $1C$ classes. The worst-case expressions of $0C$ and $1C$ classes contain two dominating exponents, which make it hard to approximate the delays in closed form. To approximate the worst-case delays in $0C$ and $1C$ classes, we need to relate the two dominating exponents. The ratio between $\tau_2$ and $\tau_3$ is given by $\frac{\tau_2}{\tau_3}=\frac{(1+\frac{3}{2}\lambda) RC (R_TC_T^\ast+R_T+C_T^\ast+(\frac{2}{\pi})^2) }{(1+3\lambda) RC(R_TC_T^\dagger+R_T+C_T^\dagger+(\frac{2}{\pi})^2)}$.
%
%We discuss the ratio for $0C$ and $1C$ as follows.
%
%\begin{enumerate}
%\item If $R_T$, $C_T^\ast$, and $C_T^\dagger$ are insignificant:
%
%This is the case we have discussed in our paper that the effect of drivers and receivers is insignificant and ignored for derivation. The ratio is given by $\frac{\tau_2}{\tau_3} \doteq \frac{1}{2}$. The worst-case delays of $0C$ and $1C$ are given by $0.165(1+3\lambda)(\frac{2}{\pi})^2 RC$ and $0.310(1+3\lambda)(\frac{2}{\pi})^2 RC$, respectively.
%
%
%\item If $R_T$ is significant, and $C_T^\ast$ and $C_T^\dagger$ are insignificant:
%
%The ratio is given by $\frac{\tau_2}{\tau_3} \doteq \frac{1}{2}$. $K^5_2 \doteq K^5_3 \doteq -1$. The worst-case delays of $0C$ and $1C$ are given by $0.093(1+3\lambda)R_S C$ and $(\ln \frac{4}{3})(1+3\lambda)R_S C$, respectively.
%
%
%\item If $R_T$ is insignificant, and $C_T^\ast$ and $C_T^\dagger$ are significant:
%
%The ratio is given by $\frac{\tau_2}{\tau_3} \doteq \frac{1}{1}$. $K^5_2 \doteq K^5_3 \doteq -1$. The worst-case delays of $0C$ and $1C$ are given by $(\ln \frac{4}{3})R C_L$ and $(\ln 2)R C_L$, respectively.
%
%
%\item If $R_T$, $C_T^\ast$, and $C_T^\dagger$ are significant:
%
%The ratio is given by $\frac{\tau_2}{\tau_3} \doteq \frac{1}{1}$. $K^5_2 \doteq K^5_3 \doteq -1$. The worst-case delays of $0C$ and $1C$ are given by $0.093 R_S C_L$ and $(\ln \frac{4}{3})R_S C_L$, respectively.
%\end{enumerate}
%
%According to the delay expressions in Tabs.~\ref{tab:3dif} and \ref{tab:5dif}, driver resistance and loading capacitance tend to increase the delay.
%
%\begin{table}
%\caption{Expressions of middle wire in a five-wire model.} \label{tab:5dif}
%\begin{center}
%\begin{tabular}{|c|c|c|}
%\hline
%$iC$ & $V_3(L,t)$ & Delay\\
%\hline
%$0C$ & $1+\frac{4}{3}K^5_2 e^{-\frac{t}{\tau_2}}-\frac{2}{3}K^5_3 e^{-\frac{t}{\tau_3}}$ & --- \\
%\hline
%$1C$ & $1+\frac{4}{3}K^5_2 e^{-\frac{t}{\tau_2}}-\frac{1}{3}K^5_3 e^{-\frac{t}{\tau_3}}$ & --- \\
%\hline
%$2C$ & $1-\frac{1}{3}K^5_1 e^{-\frac{t}{\tau_1}}+\frac{4}{3}K^5_2 e^{-\frac{t}{\tau_3}}$ & $(\ln \frac{4K^5_2}{3})\tau_2$\\
%\hline
%$3C$ & $1-K^5_3 e^{-\frac{t}{\tau_3}}$ & $(\ln 2K^5_3)\tau_3$\\
%\hline
%$4C$ & $1-\frac{1}{3}K^5_1 e^{-\frac{t}{\tau_1}}+\frac{4}{3}K^5_3 e^{-\frac{t}{\tau_3}}$ & $(\ln \frac{8K^5_3}{3})\tau_3$\\
%\hline
%\end{tabular}
%\end{center}
%\end{table}
\bibliographystyle{IEEEtran}
\bibliography{bibbus}

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Delay_model_Brief_Apr2.bbl
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