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VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb

Reinforcement Learning

text-generation

text-generation-inference

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Nellyw888 commited on May 31

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 # VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb
-For implementation details, visit our GitHub repository: [VeriReason](https://github.com/NellyW8/VeriReason)
 Check out our paper: [VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation](https://arxiv.org/abs/2505.11849)

 # VeriReason-Qwen2.5-3b-RTLCoder-Verilog-GRPO-reasoning-tb
+For implementation details, visit our GitHub repository: [VeriReason](https://github.com/NellyW8/VeriReason) and our [page](https://nellyw8.github.io/VeriReason/)
 Check out our paper: [VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation](https://arxiv.org/abs/2505.11849)