nodeConnect() {
        var x = this.absX();
        var y = this.absY();
        var n;

        for (var i = 0; i < this.parent.scope.allNodes.length; i++) {
            if (this != this.parent.scope.allNodes[i] && x == this.parent.scope.allNodes[i].absX() && y == this.parent.scope.allNodes[i].absY()) {
                n = this.parent.scope.allNodes[i];
                if (this.type == NODE_INTERMEDIATE) {
                    for (var j = 0; j < this.connections.length; j++) {
                        n.connect(this.connections[j]);
                    }
                    this.delete();
                } else {
                    this.connect(n);
                }

                break;
            }
        }

        if (n == undefined) {
            for (var i = 0; i < this.parent.scope.wires.length; i++) {
                if (this.parent.scope.wires[i].checkConvergence(this)) {
                    var n = this;
                    if (this.type != NODE_INTERMEDIATE) {
                        n = new Node(this.absX(), this.absY(), 2, this.scope.root);
                        this.connect(n);
                    }
                    this.parent.scope.wires[i].converge(n);
                    break;
                }
            }
        }
    }
if input nodde: it resolves the parent
else: it adds all the nodes onto the stack
and they are processed to generate verilog