function customResolve(clockInp, dInp, qOutput, en, masterState, 
    slaveState, prevClockState, clock_polarity, enable_polarity, numIterations) {
        
    for(var i = 0; i < numIterations; i++) {
        if(clock_polarity[i] != undefined) {
            clock_polarity[i] == true? 1 : 0;
        }
        
        if(enable_polarity[i] != undefined) {
            enable_polarity[i] == true? 1 : 0;
        }

        if(clock_polarity[i] == undefined && enable_polarity[i] == undefined) {
            if(dInp[i].value != undefined) {
                qOutput[i].value = dInp[i].value;
                simulationArea.simulationQueue.add(qOutput[i]);
            }
        }
        else if(clock_polarity[i] == undefined && enable_polarity[i] != undefined) {
            if((en_value[i] == undefined || en[i].value == enable_polarity[i]) && dInp[i].value != undefined) {
                qOutput[i].value = dInp[i].value;
                simulationArea.simulationQueue.add(qOutput[i]);
            }
        }
        else if(clock_polarity[i] != undefined && enable_polarity[i] == undefined) {
            if (clockInp[i].value == prevClockState[i]) {
                if (clockInp[i].value == 0 && dInp[i].value != undefined) {
                    masterState[i] = dInp[i].value;
                }
            } else if (clockInp[i].value != undefined) {
                if (clockInp[i].value == 1) {
                    slaveState[i] = masterState[i];
                } else if (clockInp[i].value == 0 && dInp[i].value != undefined) {
                    masterState[i] = dInp[i].value;
                }
                prevClockState[i] = clockInp[i].value;
            }

            if (qOutput[i].value != slaveState[i]) {
                qOutput[i].value = slaveState[i];
                simulationArea.simulationQueue.add(qOutput[i]);
            }
        }
        else {
            if (en[i].value == 0) {
                prevClockState[i] = clockInp[i].value;
            } else if (en[i].value == 1 || en[i].connections.length == 0) { // if(en.value==1) // Creating Infinite Loop, WHY ??
                if (clockInp[i].value == prevClockState[i]) {
                    if (clockInp[i].value == 0 && dInp[i].value != undefined) {
                        masterState[i] = dInp[i].value;
                    }
                } else if (clockInp[i].value != undefined) {
                    if (clockInp[i].value == 1) {
                        slaveState[i] = masterState[i];
                    } else if (clockInp[i].value == 0 && dInp[i].value != undefined) {
                        masterState[i] = dInp[i].value;
                    }
                    prevClockState[i] = clockInp[i].value;
                }
            }

            if (qOutput[i].value != slaveState[i]) {
                qOutput[i].value = slaveState[i];
                simulationArea.simulationQueue.add(qOutput[i]);
            }
        }
    }
}
@class
verilogRAM Component.
@extends CircuitElement
@param {number} x - x coord of element
@param {number} y - y coord of element
@param {Scope=} scope - the ciruit in which we want the Element
@param {string=} dir - direcion in which element has to drawn

Two settings are available:
- addressWidth: 1 to 20, default=10. Controls the width of the address input.
- bitWidth: 1 to 32, default=8. Controls the width of data pins.

Amount of memory in the element is 2^addressWidth x bitWidth bits.
Minimum verilogRAM size is: 2^1  x  1 = 2 bits.
Maximum verilogRAM size is: 2^20 x 32 = 1M x 32 bits => 32 Mbits => 4MB.
Maximum 8-bits size: 2^20 x  8 = 1M x 8 bits => 1MB.
Default verilogRAM size is: 2^10 x  8 = 1024 bytes => 1KB.

verilogRAMs are volatile therefore this component does not persist the memory contents.

Changes to addressWidth and bitWidth also cause data to be lost.
Think of these operations as being equivalent to taking a piece of verilogRAM out of a
circuit board and replacing it with another verilogRAM of different size.

The contents of the verilogRAM can be reset to zero by setting the RESET pin 1 or
or by selecting the component and pressing the "Reset" button in the properties window.

The contents of the verilogRAM can be dumped to the console by transitioning CORE DUMP pin to 1
or by selecting the component and pressing the "Core Dump" button in the properties window.
Address spaces that have not been written will show up as `undefined` in the core dump.

NOTE: The maximum address width of 20 is arbitrary.
Larger values are possible, but in practice circuits won't need this much
memory and keeping the value small helps avoid allocating too much memory on the browser.
Internally we use a sparse array, so only the addresses that are written are actually
allocated. Nevertheless, it is better to prevent large allocations from happening
by keeping the max addressWidth small. If needed, we can increase the max.
@category sequential