generateVerilog() {
        // Example: and and_1(_out, _out, _Q[0]);
        var inputs = [];
        var outputs = [];

        for (var i = 0; i < this.nodeList.length; i++) {
            if (this.nodeList[i].type == NODE_INPUT) {
                inputs.push(this.nodeList[i]);
            } else {
                if (this.nodeList[i].connections.length > 0)
                    outputs.push(this.nodeList[i]);
                else
                    outputs.push(""); // Don't create a wire
            }
        }

        var list = outputs.concat(inputs);
        var res = this.verilogParametrizedType();
        var moduleParams = list.map(x => x.verilogLabel).join(", ");
        res += ` ${this.verilogLabel}(${moduleParams});`;
        return res;
    }
Helper Function to generate verilog
@return {JSON}