> outb(0x06, 0x0cf9). Any idea, what I can try?
> and then reset) I get further, but it hangs somewhere in dev_enable.
> out the correct GPIOs for the former?
Ignoring the soft_reset problem, now coreboot seems to successfully finish.
The last post code is F8, so it seesm SeaBios should have been started.
#			1: the system allows a PCIE link to be established on Dev2 or Dev3.