Architecturally mapped to the AArch64 MPIDR_EL1[31:0] register. See Multiprocessor Affinity Register, EL1 for more information.
Figure 4.80 shows the MPIDR bit assignments.
Table 4.114 shows the MPIDR bit assignments.
Performance of processors at the lowest affinity level is very interdependent.
Indicates the value read in at reset, from the CLUSTERIDAFF2 configuration signal. It identifies a Cortex-A57 MPCore device in a system with more than one Cortex-A57 MPCore device present.
Indicates the value read in at reset, from the CLUSTERIDAFF1 configuration signal. It identifies an Cortex-A57 MPCore device in a system with more than one Cortex-A57 MPCore devices are present.