Q: How do I link two components from different files in VHDL? Sorry for the amount of code in advance (I added the code since I was unsure whether it is needed here to resolve my issue).
My main goal is to link two components which are in two separate .vhd files together in a block in a third file.
Lets say that I have got the following code in my file chooser.vhd:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.all;

entity chooser is
    port(
        clk, rst : in std_logic;
        DATA : in std_logic_vector(4 downto 0);
        A : out std_logic_vector(4 downto 0);
        Src : in std_logic_vector(1 downto 0);
        SOp : in std_logic_vector(1 downto 0);
        debug : out std_logic_vector(4 downto 0)
    );
end entity;

architecture structural of chooser is
-- here
begin

end architecture;

And that I have two components in another two files called registry.vhd and MUX3x5.vhd

MUX3x5.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity MUX3x5 is
    port(
        IN0 : in std_logic_vector(4 downto 0);
        IN1 : in std_logic_vector(4 downto 0);
        IN2 : in std_logic_vector(4 downto 0);
        SEL : in std_logic_vector(1 downto 0);
        O : out std_logic_vector(4 downto 0)
    );
end entity;

architecture behaviour of MUX3x5 is

...

end architecture;

registry.vhd has an output of 5 bits
I want to connect them like follows inside chooser.vhd registry --> MUX3x5  (on the second input). How do I do that in my chooser architecture above?
Should I declare them as components with their ports as seen in the entity declaration in the original files for the components in the architecture and then route them in the port map? Like so:
Attempt
architecture structural of chooser is

signal -- signals here


-- copy of the inputs/outputs in the entity declaration in the file above
component MUX3x5 is
    port(
        IN0 : in std_logic_vector(4 downto 0);
        IN1 : in std_logic_vector(4 downto 0);
        IN2 : in std_logic_vector(4 downto 0);
        SEL : in std_logic_vector(1 downto 0);
        O   : out std_logic_vector(4 downto 0)
    );
end component;


component registry is
    port(
         -- some signals here
         TS : out std_logic_vector(4 downto 0)
    );

begin

-- port map here
    port map(
            TS => IN1;
            -- other maps
);

end architecture;


A: You already have the solution. Just add the name of the entity as A.Kieffer said in his comment and make sure that the maps are separated by a , and not ;
architecture structural of chooser is

signal -- signals here
signal mux_IN0 : std_logic_vector(4 downto 0);
signal mux_IN1 : std_logic_vector(4 downto 0);
signal mux_IN2 : std_logic_vector(4 downto 0);
signal mux_SEL : std_logic_vector(1 downto 0);
signal mux_O   : std_logic_vector(4 downto 0);

-- copy of the inputs/outputs in the entity declaration in the file above
component MUX3x5 is
    port(
        IN0 : in std_logic_vector(4 downto 0);
        IN1 : in std_logic_vector(4 downto 0);
        IN2 : in std_logic_vector(4 downto 0);
        SEL : in std_logic_vector(1 downto 0);
        O   : out std_logic_vector(4 downto 0)
    );
end component;



component registry is
    port(
         -- some signals here
         TS : out std_logic_vector(4 downto 0)
    );

begin

some_name: registry
    port map(
            TS => mux_in1,    -- use , and not ;
            -- other maps
);

mux: MUX3x5
port map(
    IN0 => mux_in0,
    IN1 => mux_in1,
    IN2 => mux_in2,
    SEL => mux_sel,
    O   => mux_o
);

end architecture;

