Q: How long of a wire and how big of a load can I have for SPI bus? I have a system where I will connect up to 128 identical magnometer ICs up to an FPGA. I am trying to decide between SPI and I2C for comms. If I use SPI the setup will require 128 + 3 wires IF all sensors are on the same bus.
How do I decide/calculate if this is feasible and the sensors and wire won't load the circuit with too much capacitance or resistance?
The sensors will be distributed across several circuit boards so most of the wire length will be connecting sensor boards to each other.
I guess a general answer would be nice but just in case I am using these sensors and FPGA.


*

*https://embeddedmicro.com/tutorials/mojo/

*http://www.st.com/web/en/resource/technical/document/datasheet/DM00057547.pdf
EDIT: I appreciate any helpful advice on changing the system but what I'm looking for is how to calculate how many wires and sensors I can add before the capacitance is too great.

A: To answer your main question: No, SPI TTL or CMOS signals can not reliably drive 128 loads via off-board cables.
There is no easy calculation you can do to show this. It has to do with both loading, reflections and ground references. You can simulate the propertis of such a system, but it is a complicated waste of time.
What might work reasonably well is to use RS422 drivers and receivers specified for as many loads as you need. You also need to terminate each differential pair at the furthest end.
If you have multiple SPI slaves per board, then they can share RS422 receivers.
You also probably want to at least partially daisy chain your SPI slaves. For example, all slaves on a single board could form a chain. It will greatly reduce your cabling.
This way you will have differential signaling in your cables, which can handle more loads and is a way more reliable signaling scheme in cables.
It does however double you number of wires..
But a disclaimer is in order: No one in their right mind would design a system like this with 128+3 signaling lanes.
