Q: Verilog - re-using register value on always posedge Consider the following code:
Module Test  (B, A, CLK)

Input A, CLK;
Output B;

Reg RA;

Always @(Posedge CLK)

Begin

RA=A;
B=RA;

End
EndModule

Would that work properly to move the input to the register and then to the output on every positive edge? Can it be created with circuits?

A: It depends what you are trying to do...


*

*If you just want a single flip-flop, the simplest way is to declare reg B; then you can write always @(posedge CLK) B <= A;. There is no need for another signal.

*If (for some style reason) you want to separate the flip-flop from the output, you can wire them together with a continuous assignment assign B = RA;. The circuit would be the same.

*If you want two flip-flops (2-stage pipeline), your code is almost correct but remember to declare reg B; and use <= for both updates (they can be written in either order).

*If RA is some sort of temporary variable for describing your intentions to the tools, then Yes; you can write to it with = and use its value in the same process (do not try to access it from any other process). This is occasionally useful for e.g. accumulating things in loops, but here it would just be confusing and error-prone!
To synthesize real hardware you would typically also have a reset signal and would need to use it in the proper way for each flip-flop.

A: To answer your question, yes, what you've written (conceptually) will work. In terms of syntax, here's something that will compile and do what you're thinking. Note that I've declared your output B a register and used nonblocking assignments for the registers. 
module Test (
    input  wire CLK,
    input  wire A,
    output reg  B
);

    reg RA;

    always @(posedge CLK) begin
        RA <= A;
        B  <= RA;
    end

endmodule

